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intel/ir/gen12: Add SYNC hardware instruction. 

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2019-02-05 20:53:06 -08:00
parent 7499e10383
commit 0e57dbc55c
3 changed files with 3 additions and 0 deletions
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1
src/intel/compiler/brw_eu.cpp
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@ -467,6 +467,7 @@ enum gen {
static const struct opcode_desc opcode_descs[] = {
/* IR, HW, name, nsrc, ndst, gens */
{ BRW_OPCODE_ILLEGAL, 0, "illegal", 0, 0, GEN_ALL },
{ BRW_OPCODE_SYNC, 1, "sync", 1, 0, GEN_GE(GEN12) },
{ BRW_OPCODE_MOV, 1, "mov", 1, 1, GEN_LT(GEN12) },
{ BRW_OPCODE_MOV, 97, "mov", 1, 1, GEN_GE(GEN12) },
{ BRW_OPCODE_SEL, 2, "sel", 2, 1, GEN_LT(GEN12) },

1
src/intel/compiler/brw_eu_defines.h
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@ -197,6 +197,7 @@ enum PACKED gen10_align1_3src_dst_horizontal_stride {
enum opcode {
/* These are the actual hardware instructions. */
BRW_OPCODE_ILLEGAL,
BRW_OPCODE_SYNC,
BRW_OPCODE_MOV,
BRW_OPCODE_SEL,
BRW_OPCODE_MOVI, /**< G45+ */

1
src/intel/compiler/brw_shader.cpp
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@ -1042,6 +1042,7 @@ backend_instruction::has_side_effects() const
case SHADER_OPCODE_SEND:
return send_has_side_effects;
case BRW_OPCODE_SYNC:
case VEC4_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: