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i965/skl: Utilize new 5th bit for gateway messages 

Modify comment as spotted by Matt, and Chris Forbes

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Ben Widawsky 2016-01-26 15:44:01 -08:00
parent 34c2c7c61e
commit 0e06f76a84
1 changed files with 4 additions and 2 deletions
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6
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
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@ -924,6 +924,8 @@ void
fs_visitor::emit_barrier()
{
assert(devinfo->gen >= 7);
const uint32_t barrier_id_mask =
devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u;
/* We are getting the barrier ID from the compute shader header */
assert(stage == MESA_SHADER_COMPUTE);
@ -935,9 +937,9 @@ fs_visitor::emit_barrier()
/* Clear the message payload */
pbld.MOV(payload, brw_imm_ud(0u));
/* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
/* Copy the barrier id from r0.2 to the message payload reg.2 */
fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
pbld.AND(component(payload, 2), r0_2, brw_imm_ud(0x0f000000u));
pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask));
/* Emit a gateway "barrier" message using the payload we set up, followed
* by a wait instruction.