From 0d0affad3c37c8d2d37e5abc6fa4a9a22f7e3d86 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 29 Jan 2019 22:19:04 +0100 Subject: [PATCH] radv: don't flush src stages when dstStageMask == BOTTOM_OF_PIPE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Original patch by Fredrik Höglund. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 16 +++++++++++++++- src/amd/vulkan/radv_pass.c | 6 ++++-- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 93982c1232e..3b215b4b103 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -4646,6 +4646,7 @@ struct radv_barrier_info { uint32_t eventCount; const VkEvent *pEvents; VkPipelineStageFlags srcStageMask; + VkPipelineStageFlags dstStageMask; }; static void @@ -4697,7 +4698,19 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, image); } - radv_stage_flush(cmd_buffer, info->srcStageMask); + /* The Vulkan spec 1.1.98 says: + * + * "An execution dependency with only + * VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask + * will only prevent that stage from executing in subsequently + * submitted commands. As this stage does not perform any actual + * execution, this is not observable - in effect, it does not delay + * processing of subsequent commands. Similarly an execution dependency + * with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask + * will effectively not wait for any prior commands to complete." + */ + if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT) + radv_stage_flush(cmd_buffer, info->srcStageMask); cmd_buffer->state.flush_bits |= src_flush_bits; for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) { @@ -4738,6 +4751,7 @@ void radv_CmdPipelineBarrier( info.eventCount = 0; info.pEvents = NULL; info.srcStageMask = srcStageMask; + info.dstStageMask = destStageMask; radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers, bufferMemoryBarrierCount, pBufferMemoryBarriers, diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c index 08ea2454750..7a724dc2da5 100644 --- a/src/amd/vulkan/radv_pass.c +++ b/src/amd/vulkan/radv_pass.c @@ -47,11 +47,13 @@ radv_render_pass_add_subpass_dep(struct radv_render_pass *pass, dst = 0; if (dst == VK_SUBPASS_EXTERNAL) { - pass->end_barrier.src_stage_mask |= dep->srcStageMask; + if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT) + pass->end_barrier.src_stage_mask |= dep->srcStageMask; pass->end_barrier.src_access_mask |= dep->srcAccessMask; pass->end_barrier.dst_access_mask |= dep->dstAccessMask; } else { - pass->subpasses[dst].start_barrier.src_stage_mask |= dep->srcStageMask; + if (dep->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT) + pass->subpasses[dst].start_barrier.src_stage_mask |= dep->srcStageMask; pass->subpasses[dst].start_barrier.src_access_mask |= dep->srcAccessMask; pass->subpasses[dst].start_barrier.dst_access_mask |= dep->dstAccessMask; }