radeonsi: rename si_gfx_* functions to si_cp_*
and write_event_eop -> release_mem
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6e1cf6532d
commit
0d05581578
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@ -146,6 +146,7 @@
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#define WAIT_REG_MEM_EQUAL 3
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#define WAIT_REG_MEM_NOT_EQUAL 4
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#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4)
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#define WAIT_REG_MEM_PFP (1 << 8)
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#define PKT3_MEM_WRITE 0x3D /* not on CIK */
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#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */
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#define R_3F0_IB_BASE_LO 0x3F0
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@ -66,7 +66,7 @@ struct si_multi_fence {
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* \param old_value Previous fence value (for a bug workaround)
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* \param new_value Fence value to write for this event.
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*/
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void si_gfx_write_event_eop(struct si_context *ctx,
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void si_cp_release_mem(struct si_context *ctx,
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unsigned event, unsigned event_flags,
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unsigned dst_sel, unsigned int_sel, unsigned data_sel,
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struct r600_resource *buf, uint64_t va,
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@ -149,7 +149,7 @@ void si_gfx_write_event_eop(struct si_context *ctx,
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}
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}
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unsigned si_gfx_write_fence_dwords(struct si_screen *screen)
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unsigned si_cp_write_fence_dwords(struct si_screen *screen)
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{
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unsigned dwords = 6;
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@ -160,13 +160,13 @@ unsigned si_gfx_write_fence_dwords(struct si_screen *screen)
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return dwords;
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}
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void si_gfx_wait_fence(struct si_context *ctx,
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uint64_t va, uint32_t ref, uint32_t mask)
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void si_cp_wait_mem(struct si_context *ctx,
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uint64_t va, uint32_t ref, uint32_t mask, unsigned flags)
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{
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struct radeon_cmdbuf *cs = ctx->gfx_cs;
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1) | flags);
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radeon_emit(cs, va);
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radeon_emit(cs, va >> 32);
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radeon_emit(cs, ref); /* reference value */
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@ -275,7 +275,7 @@ static void si_fine_fence_set(struct si_context *ctx,
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radeon_emit(cs, fence_va >> 32);
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radeon_emit(cs, 0x80000000);
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} else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) {
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si_gfx_write_event_eop(ctx,
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si_cp_release_mem(ctx,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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@ -580,12 +580,12 @@ static void si_pc_emit_stop(struct si_context *sctx,
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
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si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
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EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DATA_SEL_VALUE_32BIT,
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buffer, va, 0, SI_NOT_QUERY);
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si_gfx_wait_fence(sctx, va, 0, 0xffffffff);
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si_cp_wait_mem(sctx, va, 0, 0xffffffff, 0);
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));
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@ -684,7 +684,7 @@ void si_init_perfcounters(struct si_screen *screen)
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if (!pc)
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return;
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pc->num_stop_cs_dwords = 14 + si_gfx_write_fence_dwords(screen);
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pc->num_stop_cs_dwords = 14 + si_cp_write_fence_dwords(screen);
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pc->num_instance_cs_dwords = 3;
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pc->num_shader_types = ARRAY_SIZE(si_pc_shader_type_bits);
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@ -1170,14 +1170,14 @@ void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst
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uint64_t offset, uint64_t size, unsigned value);
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/* si_fence.c */
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void si_gfx_write_event_eop(struct si_context *ctx,
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void si_cp_release_mem(struct si_context *ctx,
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unsigned event, unsigned event_flags,
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unsigned dst_sel, unsigned int_sel, unsigned data_sel,
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struct r600_resource *buf, uint64_t va,
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uint32_t new_fence, unsigned query_type);
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unsigned si_gfx_write_fence_dwords(struct si_screen *screen);
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void si_gfx_wait_fence(struct si_context *ctx,
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uint64_t va, uint32_t ref, uint32_t mask);
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unsigned si_cp_write_fence_dwords(struct si_screen *screen);
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void si_cp_wait_mem(struct si_context *ctx,
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uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
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void si_init_fence_functions(struct si_context *ctx);
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void si_init_screen_fence_functions(struct si_screen *screen);
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struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
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@ -665,7 +665,7 @@ static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
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case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
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query->result_size = 16 * sscreen->info.num_render_backends;
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query->result_size += 16; /* for the fence + alignment */
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query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
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query->num_cs_dw_end = 6 + si_cp_write_fence_dwords(sscreen);
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break;
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case SI_QUERY_TIME_ELAPSED_SDMA:
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/* GET_GLOBAL_TIMESTAMP only works if the offset is a multiple of 32. */
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@ -674,11 +674,11 @@ static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
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break;
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case PIPE_QUERY_TIME_ELAPSED:
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query->result_size = 24;
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query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
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query->num_cs_dw_end = 8 + si_cp_write_fence_dwords(sscreen);
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break;
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case PIPE_QUERY_TIMESTAMP:
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query->result_size = 16;
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query->num_cs_dw_end = 8 + si_gfx_write_fence_dwords(sscreen);
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query->num_cs_dw_end = 8 + si_cp_write_fence_dwords(sscreen);
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query->flags = SI_QUERY_HW_FLAG_NO_START;
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break;
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case PIPE_QUERY_PRIMITIVES_EMITTED:
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@ -699,7 +699,7 @@ static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
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/* 11 values on GCN. */
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query->result_size = 11 * 16;
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query->result_size += 8; /* for the fence + alignment */
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query->num_cs_dw_end = 6 + si_gfx_write_fence_dwords(sscreen);
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query->num_cs_dw_end = 6 + si_cp_write_fence_dwords(sscreen);
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break;
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default:
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assert(0);
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@ -890,7 +890,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx,
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va += 8;
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/* fall through */
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case PIPE_QUERY_TIMESTAMP:
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si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS,
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si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS,
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0, EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DATA_SEL_TIMESTAMP, NULL, va,
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@ -916,7 +916,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx,
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RADEON_PRIO_QUERY);
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if (fence_va) {
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si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
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si_cp_release_mem(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
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EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DATA_SEL_VALUE_32BIT,
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@ -1580,7 +1580,7 @@ static void si_query_hw_get_result_resource(struct si_context *sctx,
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va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
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va += params.fence_offset;
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si_gfx_wait_fence(sctx, va, 0x80000000, 0x80000000);
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si_cp_wait_mem(sctx, va, 0x80000000, 0x80000000, 0);
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}
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sctx->b.launch_grid(&sctx->b, &grid);
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@ -918,7 +918,7 @@ void si_emit_cache_flush(struct si_context *sctx)
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/* Necessary for DCC */
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if (sctx->chip_class == VI)
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si_gfx_write_event_eop(sctx,
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si_cp_release_mem(sctx,
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V_028A90_FLUSH_AND_INV_CB_DATA_TS,
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0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
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EOP_DATA_SEL_DISCARD, NULL,
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@ -1035,13 +1035,13 @@ void si_emit_cache_flush(struct si_context *sctx)
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va = sctx->wait_mem_scratch->gpu_address;
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sctx->wait_mem_number++;
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si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
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si_cp_release_mem(sctx, cb_db_event, tc_flags,
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EOP_DST_SEL_MEM,
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EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
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EOP_DATA_SEL_VALUE_32BIT,
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sctx->wait_mem_scratch, va,
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sctx->wait_mem_number, SI_NOT_QUERY);
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si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
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si_cp_wait_mem(sctx, va, sctx->wait_mem_number, 0xffffffff, 0);
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}
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/* Make sure ME is idle (it executes most packets) before continuing.
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