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aco: simplify consecutive ordered vmem/lds writes optimization 

This was unnecessary and messed with statistics

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4949>
This commit is contained in:
Rhys Perry 2020-05-07 15:02:20 +01:00 committed by Marge Bot
parent a6beb051af
commit 0c7bed72f7
1 changed files with 2 additions and 10 deletions
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12
src/amd/compiler/aco_insert_waitcnt.cpp
View File

@ -402,22 +402,14 @@ wait_imm check_instr(Instruction* instr, wait_ctx& ctx)
continue;
/* Vector Memory reads and writes return in the order they were issued */
if (instr->isVMEM() && ((it->second.events & vm_events) == event_vmem)) {
it->second.remove_counter(counter_vm);
if (!it->second.counters)
it = ctx.gpr_map.erase(it);
if (instr->isVMEM() && ((it->second.events & vm_events) == event_vmem))
continue;
}
/* LDS reads and writes return in the order they were issued. same for GDS */
if (instr->format == Format::DS) {
bool gds = static_cast<DS_instruction*>(instr)->gds;
if ((it->second.events & lgkm_events) == (gds ? event_gds : event_lds)) {
it->second.remove_counter(counter_lgkm);
if (!it->second.counters)
it = ctx.gpr_map.erase(it);
if ((it->second.events & lgkm_events) == (gds ? event_gds : event_lds))
continue;
}
}
wait.combine(it->second.imm);