radeon: move some functions to r600_buffer_common.c
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christoph Brill <egore911@gmail.com>
v2: Renamed r600_buffer.c to r600_buffer_common.c. The stupid build system
doesn't allow 2 files of the same name in different directories.
This commit is contained in:
Marek Olšák
parent
0b37737cc3
commit
0aea43db93
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@ -1,4 +1,5 @@
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C_SOURCES := \
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r600_buffer_common.c \
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r600_pipe_common.c \
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r600_streamout.c \
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r600_texture.c \
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@ -0,0 +1,148 @@
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Marek Olšák
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*/
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#include "r600_cs.h"
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#include <inttypes.h>
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boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
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struct radeon_winsys_cs_handle *buf,
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enum radeon_bo_usage usage)
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{
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if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
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return TRUE;
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}
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if (ctx->rings.dma.cs &&
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ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
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return TRUE;
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}
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return FALSE;
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}
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void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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struct r600_resource *resource,
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unsigned usage)
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{
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enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
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if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
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return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
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}
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if (!(usage & PIPE_TRANSFER_WRITE)) {
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/* have to wait for the last write */
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rusage = RADEON_USAGE_WRITE;
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}
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if (ctx->rings.gfx.cs->cdw &&
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ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
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resource->cs_buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
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return NULL;
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} else {
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ctx->rings.gfx.flush(ctx, 0);
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}
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}
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if (ctx->rings.dma.cs &&
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ctx->rings.dma.cs->cdw &&
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ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
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resource->cs_buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
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return NULL;
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} else {
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ctx->rings.dma.flush(ctx, 0);
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}
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}
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if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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return NULL;
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} else {
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/* We will be wait for the GPU. Wait for any offloaded
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* CS flush to complete to avoid busy-waiting in the winsys. */
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ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
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if (ctx->rings.dma.cs)
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ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
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}
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}
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return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
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}
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bool r600_init_resource(struct r600_common_screen *rscreen,
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struct r600_resource *res,
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unsigned size, unsigned alignment,
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bool use_reusable_pool, unsigned usage)
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{
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uint32_t initial_domain, domains;
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switch(usage) {
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case PIPE_USAGE_STAGING:
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/* Staging resources participate in transfers, i.e. are used
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* for uploads and downloads from regular resources.
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* We generate them internally for some transfers.
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*/
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initial_domain = RADEON_DOMAIN_GTT;
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domains = RADEON_DOMAIN_GTT;
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break;
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case PIPE_USAGE_DYNAMIC:
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case PIPE_USAGE_STREAM:
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/* Default to GTT, but allow the memory manager to move it to VRAM. */
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initial_domain = RADEON_DOMAIN_GTT;
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domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
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break;
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case PIPE_USAGE_DEFAULT:
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case PIPE_USAGE_STATIC:
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case PIPE_USAGE_IMMUTABLE:
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default:
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/* Don't list GTT here, because the memory manager would put some
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* resources to GTT no matter what the initial domain is.
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* Not listing GTT in the domains improves performance a lot. */
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initial_domain = RADEON_DOMAIN_VRAM;
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domains = RADEON_DOMAIN_VRAM;
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break;
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}
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res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
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use_reusable_pool,
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initial_domain);
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if (!res->buf) {
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return false;
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}
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res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
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res->domains = domains;
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util_range_set_empty(&res->valid_buffer_range);
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if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
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fprintf(stderr, "VM start=0x%"PRIu64" end=0x%"PRIu64" | Buffer %u bytes\n",
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r600_resource_va(&rscreen->b, &res->b.b),
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r600_resource_va(&rscreen->b, &res->b.b) + res->buf->size,
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res->buf->size);
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}
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return true;
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}
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@ -306,123 +306,3 @@ void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_re
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rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
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pipe_mutex_unlock(rscreen->aux_context_lock);
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}
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boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
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struct radeon_winsys_cs_handle *buf,
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enum radeon_bo_usage usage)
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{
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if (ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs, buf, usage)) {
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return TRUE;
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}
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if (ctx->rings.dma.cs &&
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ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs, buf, usage)) {
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return TRUE;
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}
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return FALSE;
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}
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void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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struct r600_resource *resource,
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unsigned usage)
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{
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enum radeon_bo_usage rusage = RADEON_USAGE_READWRITE;
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if (usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
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return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
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}
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if (!(usage & PIPE_TRANSFER_WRITE)) {
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/* have to wait for the last write */
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rusage = RADEON_USAGE_WRITE;
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}
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if (ctx->rings.gfx.cs->cdw &&
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ctx->ws->cs_is_buffer_referenced(ctx->rings.gfx.cs,
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resource->cs_buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
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return NULL;
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} else {
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ctx->rings.gfx.flush(ctx, 0);
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}
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}
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if (ctx->rings.dma.cs &&
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ctx->rings.dma.cs->cdw &&
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ctx->ws->cs_is_buffer_referenced(ctx->rings.dma.cs,
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resource->cs_buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
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return NULL;
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} else {
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ctx->rings.dma.flush(ctx, 0);
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}
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}
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if (ctx->ws->buffer_is_busy(resource->buf, rusage)) {
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if (usage & PIPE_TRANSFER_DONTBLOCK) {
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return NULL;
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} else {
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/* We will be wait for the GPU. Wait for any offloaded
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* CS flush to complete to avoid busy-waiting in the winsys. */
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ctx->ws->cs_sync_flush(ctx->rings.gfx.cs);
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if (ctx->rings.dma.cs)
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ctx->ws->cs_sync_flush(ctx->rings.dma.cs);
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}
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}
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return ctx->ws->buffer_map(resource->cs_buf, NULL, usage);
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}
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bool r600_init_resource(struct r600_common_screen *rscreen,
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struct r600_resource *res,
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unsigned size, unsigned alignment,
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bool use_reusable_pool, unsigned usage)
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{
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uint32_t initial_domain, domains;
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switch(usage) {
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case PIPE_USAGE_STAGING:
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/* Staging resources participate in transfers, i.e. are used
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* for uploads and downloads from regular resources.
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* We generate them internally for some transfers.
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*/
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initial_domain = RADEON_DOMAIN_GTT;
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domains = RADEON_DOMAIN_GTT;
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break;
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case PIPE_USAGE_DYNAMIC:
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case PIPE_USAGE_STREAM:
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/* Default to GTT, but allow the memory manager to move it to VRAM. */
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initial_domain = RADEON_DOMAIN_GTT;
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domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
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break;
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case PIPE_USAGE_DEFAULT:
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case PIPE_USAGE_STATIC:
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case PIPE_USAGE_IMMUTABLE:
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default:
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/* Don't list GTT here, because the memory manager would put some
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* resources to GTT no matter what the initial domain is.
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* Not listing GTT in the domains improves performance a lot. */
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initial_domain = RADEON_DOMAIN_VRAM;
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domains = RADEON_DOMAIN_VRAM;
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break;
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}
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res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
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use_reusable_pool,
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initial_domain);
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if (!res->buf) {
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return false;
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}
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res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
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res->domains = domains;
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util_range_set_empty(&res->valid_buffer_range);
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if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
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fprintf(stderr, "VM start=0x%"PRIu64" end=0x%"PRIu64" | Buffer %u bytes\n",
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r600_resource_va(&rscreen->b, &res->b.b),
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r600_resource_va(&rscreen->b, &res->b.b) + res->buf->size,
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res->buf->size);
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}
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return true;
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}
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@ -255,6 +255,18 @@ struct r600_common_context {
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unsigned first_sample, unsigned last_sample);
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};
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/* r600_buffer.c */
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boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
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struct radeon_winsys_cs_handle *buf,
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enum radeon_bo_usage usage);
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void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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struct r600_resource *resource,
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unsigned usage);
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bool r600_init_resource(struct r600_common_screen *rscreen,
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struct r600_resource *res,
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unsigned size, unsigned alignment,
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bool use_reusable_pool, unsigned usage);
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/* r600_common_pipe.c */
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bool r600_common_screen_init(struct r600_common_screen *rscreen,
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struct radeon_winsys *ws);
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@ -267,16 +279,6 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen,
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const struct tgsi_token *tokens);
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void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
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unsigned offset, unsigned size, unsigned value);
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boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
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struct radeon_winsys_cs_handle *buf,
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enum radeon_bo_usage usage);
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void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
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struct r600_resource *resource,
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unsigned usage);
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bool r600_init_resource(struct r600_common_screen *rscreen,
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struct r600_resource *res,
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unsigned size, unsigned alignment,
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bool use_reusable_pool, unsigned usage);
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/* r600_streamout.c */
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void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
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