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r600g: Only update DB_SHADER_CONTROL once in r600_pipe_shader_ps(). 

Avoid setting the same gpu register several times in a r600_pipe_state.
Compute the final value of the register and set that one time. This avoids
some overhead in r600_context_pipe_state_set().

Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Signed-off-by: Henri Verbeet <hverbeet@gmail.com>
This commit is contained in:
Mathias Fröhlich 2011-02-27 07:11:27 +01:00 committed by Henri Verbeet
parent 629bc76b75
commit 0a6f09a76a
1 changed files with 13 additions and 16 deletions
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29
src/gallium/drivers/r600/r600_shader.c
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@ -101,7 +101,7 @@ static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shade
{
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
int pos_index = -1, face_index = -1;
rstate->nregs = 0;
@ -113,18 +113,15 @@ static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shade
face_index = i;
}
db_shader_control = 0;
for (i = 0; i < rshader->noutput; i++) {
if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
r600_pipe_state_add_reg(rstate,
R_02880C_DB_SHADER_CONTROL,
S_02880C_Z_EXPORT_ENABLE(1),
S_02880C_Z_EXPORT_ENABLE(1), NULL);
db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
r600_pipe_state_add_reg(rstate,
R_02880C_DB_SHADER_CONTROL,
S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
}
if (rshader->uses_kill)
db_shader_control |= S_02880C_KILL_ENABLE(1);
exports_ps = 0;
num_cout = 0;
@ -182,14 +179,14 @@ static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shade
S_028808_MULTIWRITE_ENABLE(1),
NULL);
}
/* only set some bits here, the other bits are set in the dsa state */
r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
db_shader_control,
S_02880C_Z_EXPORT_ENABLE(1) |
S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
S_02880C_KILL_ENABLE(1),
NULL);
if (rshader->uses_kill) {
/* only set some bits here, the other bits are set in the dsa state */
r600_pipe_state_add_reg(rstate,
R_02880C_DB_SHADER_CONTROL,
S_02880C_KILL_ENABLE(1),
S_02880C_KILL_ENABLE(1), NULL);
}
r600_pipe_state_add_reg(rstate,
R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
0xFFFFFFFF, NULL);