intel/fs/gen11+: Handle ROR/ROL in lower_simd_width().
Prevents invalid code from being emitted for ROR/ROL instructions in
SIMD32 shaders.
The problem can be reproduced with the following tests while forcing
SIMD32 to be used for fragment shaders:
piglit.shaders.glsl-rotate-left
piglit.shaders.glsl-rotate-right
However the issue could occur in production already with compute
shaders and a workgroup size large enough to trigger SIMD32 dispatch.
Fixes: 83fdec0f0d
"intel/compiler: Enable the emission of ROR/ROL instructions"
Cc: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -6237,6 +6237,8 @@ get_lowered_simd_width(const struct gen_device_info *devinfo,
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case BRW_OPCODE_SHR:
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case BRW_OPCODE_SHL:
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case BRW_OPCODE_ASR:
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case BRW_OPCODE_ROR:
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case BRW_OPCODE_ROL:
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case BRW_OPCODE_CMPN:
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case BRW_OPCODE_CSEL:
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case BRW_OPCODE_F32TO16:
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