intel/blorp: Always emit URB config on Gen7+
Previously, i965/iris tried to reuse the currently programmed URB config if it was good enough for BLORP, rather than reprogramming it each time. However, this will make some things harder on Gen12+ and we've not seen any performance impact from emitting URB more frequently in ANV. This makes the blorp <-> driver interface a bit simpler on Gen7+ because now all the driver has to do is to provide the L3$ config rather than trying to hand off URB re-config to blorp. Cc: "20.0" mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
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09e4c33085
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@ -247,24 +247,11 @@ blorp_flush_range(UNUSED struct blorp_batch *blorp_batch,
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*/
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*/
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}
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}
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static void
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static const struct gen_l3_config *
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blorp_emit_urb_config(struct blorp_batch *blorp_batch,
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blorp_get_l3_config(struct blorp_batch *blorp_batch)
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unsigned vs_entry_size,
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UNUSED unsigned sf_entry_size)
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{
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{
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struct iris_context *ice = blorp_batch->blorp->driver_ctx;
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struct iris_batch *batch = blorp_batch->driver_batch;
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struct iris_batch *batch = blorp_batch->driver_batch;
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return batch->screen->l3_config_3d;
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unsigned size[4] = { vs_entry_size, 1, 1, 1 };
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/* If last VS URB size is good enough for what the BLORP operation needed,
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* then we can skip reconfiguration
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*/
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if (ice->shaders.last_vs_entry_size >= vs_entry_size)
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return;
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genX(emit_urb_setup)(ice, batch, size, false, false);
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ice->state.dirty |= IRIS_DIRTY_URB;
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}
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}
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static void
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static void
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@ -346,7 +333,6 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
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IRIS_DIRTY_UNCOMPILED_GS |
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IRIS_DIRTY_UNCOMPILED_GS |
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IRIS_DIRTY_UNCOMPILED_FS |
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IRIS_DIRTY_UNCOMPILED_FS |
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IRIS_DIRTY_VF |
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IRIS_DIRTY_VF |
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IRIS_DIRTY_URB |
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IRIS_DIRTY_SF_CL_VIEWPORT |
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IRIS_DIRTY_SF_CL_VIEWPORT |
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IRIS_DIRTY_SAMPLER_STATES_VS |
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IRIS_DIRTY_SAMPLER_STATES_VS |
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IRIS_DIRTY_SAMPLER_STATES_TCS |
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IRIS_DIRTY_SAMPLER_STATES_TCS |
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@ -27,6 +27,7 @@
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#include "blorp_priv.h"
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#include "blorp_priv.h"
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#include "dev/gen_device_info.h"
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#include "dev/gen_device_info.h"
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#include "common/gen_sample_positions.h"
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#include "common/gen_sample_positions.h"
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#include "common/gen_l3_config.h"
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#include "genxml/gen_macros.h"
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#include "genxml/gen_macros.h"
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/**
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/**
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@ -65,10 +66,8 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
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uint32_t *sizes,
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uint32_t *sizes,
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unsigned num_vbs);
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unsigned num_vbs);
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#if GEN_GEN >= 8
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UNUSED static struct blorp_address
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static struct blorp_address
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blorp_get_workaround_page(struct blorp_batch *batch);
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blorp_get_workaround_page(struct blorp_batch *batch);
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#endif
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static void
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static void
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blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
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blorp_alloc_binding_table(struct blorp_batch *batch, unsigned num_entries,
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@ -92,9 +91,14 @@ static struct blorp_address
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blorp_get_surface_base_address(struct blorp_batch *batch);
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blorp_get_surface_base_address(struct blorp_batch *batch);
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#endif
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#endif
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#if GEN_GEN >= 7
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static const struct gen_l3_config *
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blorp_get_l3_config(struct blorp_batch *batch);
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# else
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static void
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static void
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blorp_emit_urb_config(struct blorp_batch *batch,
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blorp_emit_urb_config(struct blorp_batch *batch,
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unsigned vs_entry_size, unsigned sf_entry_size);
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unsigned vs_entry_size, unsigned sf_entry_size);
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#endif
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static void
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static void
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blorp_emit_pipeline(struct blorp_batch *batch,
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blorp_emit_pipeline(struct blorp_batch *batch,
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@ -207,7 +211,42 @@ emit_urb_config(struct blorp_batch *batch,
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const unsigned sf_entry_size =
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const unsigned sf_entry_size =
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params->sf_prog_data ? params->sf_prog_data->urb_entry_size : 0;
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params->sf_prog_data ? params->sf_prog_data->urb_entry_size : 0;
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#if GEN_GEN >= 7
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assert(sf_entry_size == 0);
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const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
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unsigned entries[4], start[4];
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gen_get_urb_config(batch->blorp->compiler->devinfo,
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blorp_get_l3_config(batch),
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false, false, entry_size, entries, start);
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#if GEN_GEN == 7 && !GEN_IS_HASWELL
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/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
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*
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* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
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* needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
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* 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
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* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
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* needs to be sent before any combination of VS associated 3DSTATE."
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*/
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blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
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pc.DepthStallEnable = true;
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pc.PostSyncOperation = WriteImmediateData;
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pc.Address = blorp_get_workaround_page(batch);
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}
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#endif
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for (int i = 0; i <= MESA_SHADER_GEOMETRY; i++) {
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blorp_emit(batch, GENX(3DSTATE_URB_VS), urb) {
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urb._3DCommandSubOpcode += i;
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urb.VSURBStartingAddress = start[i];
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urb.VSURBEntryAllocationSize = entry_size[i] - 1;
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urb.VSNumberofURBEntries = entries[i];
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}
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}
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#else /* GEN_GEN < 7 */
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blorp_emit_urb_config(batch, vs_entry_size, sf_entry_size);
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blorp_emit_urb_config(batch, vs_entry_size, sf_entry_size);
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#endif
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}
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}
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#if GEN_GEN >= 7
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#if GEN_GEN >= 7
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@ -178,8 +178,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
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(1 << num_vbs) - 1);
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(1 << num_vbs) - 1);
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}
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}
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#if GEN_GEN >= 8
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UNUSED static struct blorp_address
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static struct blorp_address
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blorp_get_workaround_page(struct blorp_batch *batch)
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blorp_get_workaround_page(struct blorp_batch *batch)
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{
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{
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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@ -188,7 +187,6 @@ blorp_get_workaround_page(struct blorp_batch *batch)
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.buffer = cmd_buffer->device->workaround_bo,
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.buffer = cmd_buffer->device->workaround_bo,
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};
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};
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}
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}
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#endif
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static void
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static void
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blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
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blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
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@ -197,22 +195,11 @@ blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
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*/
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*/
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}
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}
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static void
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static const struct gen_l3_config *
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blorp_emit_urb_config(struct blorp_batch *batch,
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blorp_get_l3_config(struct blorp_batch *batch)
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unsigned vs_entry_size, unsigned sf_entry_size)
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{
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{
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struct anv_device *device = batch->blorp->driver_ctx;
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
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return cmd_buffer->state.current_l3_config;
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assert(sf_entry_size == 0);
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const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 };
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genX(emit_urb_setup)(device, &cmd_buffer->batch,
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cmd_buffer->state.current_l3_config,
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VK_SHADER_STAGE_VERTEX_BIT |
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VK_SHADER_STAGE_FRAGMENT_BIT,
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entry_size);
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}
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}
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void
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void
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@ -231,8 +231,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
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#endif
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#endif
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}
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}
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#if GEN_GEN >= 8
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UNUSED static struct blorp_address
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static struct blorp_address
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blorp_get_workaround_page(struct blorp_batch *batch)
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blorp_get_workaround_page(struct blorp_batch *batch)
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{
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{
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assert(batch->blorp->driver_ctx == batch->driver_batch);
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assert(batch->blorp->driver_ctx == batch->driver_batch);
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@ -242,7 +241,6 @@ blorp_get_workaround_page(struct blorp_batch *batch)
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.buffer = brw->workaround_bo,
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.buffer = brw->workaround_bo,
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};
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};
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}
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}
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#endif
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static void
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static void
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blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start,
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blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start,
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@ -253,6 +251,16 @@ blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start,
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*/
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*/
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}
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}
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#if GEN_GEN >= 7
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static const struct gen_l3_config *
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blorp_get_l3_config(struct blorp_batch *batch)
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{
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assert(batch->blorp->driver_ctx == batch->driver_batch);
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struct brw_context *brw = batch->driver_batch;
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return brw->l3.config;
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}
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#else /* GEN_GEN < 7 */
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static void
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static void
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blorp_emit_urb_config(struct blorp_batch *batch,
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blorp_emit_urb_config(struct blorp_batch *batch,
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unsigned vs_entry_size,
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unsigned vs_entry_size,
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@ -261,18 +269,14 @@ blorp_emit_urb_config(struct blorp_batch *batch,
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assert(batch->blorp->driver_ctx == batch->driver_batch);
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assert(batch->blorp->driver_ctx == batch->driver_batch);
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struct brw_context *brw = batch->driver_batch;
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struct brw_context *brw = batch->driver_batch;
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#if GEN_GEN >= 7
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#if GEN_GEN == 6
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if (brw->urb.vsize >= vs_entry_size)
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return;
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gen7_upload_urb(brw, vs_entry_size, false, false);
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#elif GEN_GEN == 6
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gen6_upload_urb(brw, vs_entry_size, false, 0);
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gen6_upload_urb(brw, vs_entry_size, false, 0);
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#else
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#else
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/* We calculate it now and emit later. */
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/* We calculate it now and emit later. */
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brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size);
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brw_calculate_urb_fence(brw, 0, vs_entry_size, sf_entry_size);
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#endif
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#endif
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}
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}
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#endif
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void
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void
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genX(blorp_exec)(struct blorp_batch *batch,
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genX(blorp_exec)(struct blorp_batch *batch,
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@ -387,6 +391,12 @@ retry:
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brw->no_depth_or_stencil = !params->depth.enabled &&
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brw->no_depth_or_stencil = !params->depth.enabled &&
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!params->stencil.enabled;
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!params->stencil.enabled;
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brw->ib.index_size = -1;
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brw->ib.index_size = -1;
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brw->urb.vsize = 0;
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brw->urb.gs_present = false;
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brw->urb.gsize = 0;
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brw->urb.tess_present = false;
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brw->urb.hsize = 0;
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brw->urb.dsize = 0;
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if (params->dst.enabled) {
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if (params->dst.enabled) {
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brw_render_cache_add_bo(brw, params->dst.addr.buffer,
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brw_render_cache_add_bo(brw, params->dst.addr.buffer,
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