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util/threaded_context: use driver's buffer alignment for staging transfers 

this coincidentally worked because radeonsi has a hardcoded value of 64, but
other drivers do not use this value and then things are subtly broken

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7452>
This commit is contained in:
Mike Blumenkrantz 2020-11-04 17:48:21 -05:00 committed by Marge Bot
parent 60b9c00afd
commit 092186d985
1 changed files with 2 additions and 1 deletions
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3
src/gallium/auxiliary/util/u_threaded_context.c
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@ -1566,7 +1566,8 @@ tc_transfer_map(struct pipe_context *_pipe,
u_upload_alloc(tc->base.stream_uploader, 0,
box->width + (box->x % tc->map_buffer_alignment),
64, &ttrans->offset, &ttrans->staging, (void**)&map);
tc->map_buffer_alignment, &ttrans->offset,
&ttrans->staging, (void**)&map);
if (!map) {
slab_free(&tc->pool_transfers, ttrans);
return NULL;