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radeonsi: flush TC L2 before using a compute indirect buffer 

There is no known test for this.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-09-08 20:15:51 +02:00
parent a5a2cc530c
commit 08bcbfdc07
1 changed files with 10 additions and 2 deletions
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12
src/gallium/drivers/radeonsi/si_compute.c
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@ -464,10 +464,18 @@ static void si_launch_grid(
/* Add buffer sizes for memory checking in need_cs_space. */
r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
if (info->indirect)
r600_context_add_resource_size(ctx, info->indirect);
/* TODO: add the scratch buffer */
if (info->indirect) {
r600_context_add_resource_size(ctx, info->indirect);
/* The hw doesn't read the indirect buffer via TC L2. */
if (r600_resource(info->indirect)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
r600_resource(info->indirect)->TC_L2_dirty = false;
}
}
si_need_cs_space(sctx);
if (!sctx->cs_shader_state.initialized)