nir: Split ALU instructions in loops that read phis
A single shader in Unigine Superposition is affected by this change.
A single iadd is moved to the end of a loop. This iadd is involved in
a complex set of logic to terminate the loop, and an extra mov
instruction is inserted. This shader really needs the optimization
suggested by bugzilla #94747, and I expect that to make this tiny
regression go away.
All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15047543 -> 15047545 (<.01%)
instructions in affected programs: 565 -> 567 (0.35%)
helped: 0
HURT: 2
total cycles in shared programs: 369977253 -> 369978253 (<.01%)
cycles in affected programs: 127910 -> 128910 (0.78%)
helped: 0
HURT: 2
v2: Skip nir_op_vec{2,3,4} and nir_op_[fi]mov instructions to avoid
infinite optimization loops. Remove the original ALU instruciton after
all of its readers are modified to read the new ALU instruction.
v3: Extend to the more general case. The if the prev-block value from
the phi is not undef, this means the ALU instruction has to be
duplicated in both the prev-block and the continue-block.
Fixes: 8fb8ebfbb0 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
Ian Romanick
parent
0c0c69729b
commit
0881e90c09
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@ -27,6 +27,10 @@
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#include "nir_control_flow.h"
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#include "nir_loop_analyze.h"
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static nir_ssa_def *clone_alu_and_replace_src_defs(nir_builder *b,
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const nir_alu_instr *alu,
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nir_ssa_def **src_defs);
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/**
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* Gets the single block that jumps back to the loop header. Already assumes
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* there is exactly one such block.
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@ -249,6 +253,295 @@ opt_peel_loop_initial_if(nir_loop *loop)
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return true;
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}
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static bool
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alu_instr_is_comparison(const nir_alu_instr *alu)
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{
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switch (alu->op) {
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case nir_op_flt32:
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case nir_op_fge32:
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case nir_op_feq32:
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case nir_op_fne32:
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case nir_op_ilt32:
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case nir_op_ult32:
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case nir_op_ige32:
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case nir_op_uge32:
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case nir_op_ieq32:
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case nir_op_ine32:
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return true;
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default:
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return nir_alu_instr_is_comparison(alu);
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}
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}
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static bool
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alu_instr_is_type_conversion(const nir_alu_instr *alu)
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{
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return nir_op_infos[alu->op].num_inputs == 1 &&
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nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) !=
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nir_alu_type_get_base_type(nir_op_infos[alu->op].input_types[0]);
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}
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/**
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* Splits ALU instructions that have a source that is a phi node
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*
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* ALU instructions in the header block of a loop that meet the following
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* criteria can be split.
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*
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* - The loop has no continue instructions other than the "natural" continue
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* at the bottom of the loop.
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*
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* - At least one source of the instruction is a phi node from the header block.
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*
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* and either this rule
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*
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* - The phi node selects undef from the block before the loop and a value
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* from the continue block of the loop.
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*
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* or these two rules
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*
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* - The phi node selects a constant from the block before the loop.
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*
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* - The non-phi source of the ALU instruction comes from a block that
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* dominates the block before the loop. The most common failure mode for
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* this check is sources that are generated in the loop header block.
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*
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* The split process moves the original ALU instruction to the bottom of the
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* loop. The phi node source is replaced with the value from the phi node
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* selected from the continue block (i.e., the non-undef value). A new phi
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* node is added to the header block that selects either undef from the block
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* before the loop or the result of the (moved) ALU instruction.
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*
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* The splitting transforms a loop like:
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*
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* vec1 32 ssa_7 = undefined
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* vec1 32 ssa_8 = load_const (0x00000001)
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* vec1 32 ssa_10 = load_const (0x00000000)
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* // succs: block_1
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* loop {
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* block block_1:
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* // preds: block_0 block_4
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* vec1 32 ssa_11 = phi block_0: ssa_7, block_4: ssa_15
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* vec1 32 ssa_12 = phi block_0: ssa_1, block_4: ssa_15
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* vec1 32 ssa_13 = phi block_0: ssa_10, block_4: ssa_16
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* vec1 32 ssa_14 = iadd ssa_11, ssa_8
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* vec1 32 ssa_15 = b32csel ssa_13, ssa_14, ssa_12
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* ...
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* // succs: block_1
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* }
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*
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* into:
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*
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* vec1 32 ssa_7 = undefined
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* vec1 32 ssa_8 = load_const (0x00000001)
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* vec1 32 ssa_10 = load_const (0x00000000)
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* // succs: block_1
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* loop {
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* block block_1:
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* // preds: block_0 block_4
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* vec1 32 ssa_11 = phi block_0: ssa_7, block_4: ssa_15
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* vec1 32 ssa_12 = phi block_0: ssa_1, block_4: ssa_15
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* vec1 32 ssa_13 = phi block_0: ssa_10, block_4: ssa_16
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* vec1 32 ssa_21 = phi block_0: sss_7, block_4: ssa_20
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* vec1 32 ssa_15 = b32csel ssa_13, ssa_21, ssa_12
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* ...
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* vec1 32 ssa_20 = iadd ssa_15, ssa_8
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* // succs: block_1
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* }
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*
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* If the phi does not select an undef, the instruction is duplicated in the
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* loop continue block (as in the undef case) and in the previous block. When
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* the ALU instruction is duplicated in the previous block, the correct source
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* must be selected from the phi node.
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*/
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static bool
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opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
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{
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bool progress = false;
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nir_block *header_block = nir_loop_first_block(loop);
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nir_block *const prev_block =
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nir_cf_node_as_block(nir_cf_node_prev(&loop->cf_node));
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/* It would be insane if this were not true */
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assert(_mesa_set_search(header_block->predecessors, prev_block));
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/* The loop must have exactly one continue block which could be a block
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* ending in a continue instruction or the "natural" continue from the
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* last block in the loop back to the top.
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*/
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if (header_block->predecessors->entries != 2)
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return false;
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nir_foreach_instr_safe(instr, header_block) {
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if (instr->type != nir_instr_type_alu)
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continue;
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nir_alu_instr *const alu = nir_instr_as_alu(instr);
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/* Most ALU ops produce an undefined result if any source is undef.
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* However, operations like bcsel only produce undefined results of the
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* first operand is undef. Even in the undefined case, the result
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* should be one of the other two operands, so the result of the bcsel
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* should never be replaced with undef.
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*
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* nir_op_vec{2,3,4}, nir_op_imov, and nir_op_fmov are excluded because
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* they can easily lead to infinite optimization loops.
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*/
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if (alu->op == nir_op_bcsel ||
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alu->op == nir_op_b32csel ||
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alu->op == nir_op_fcsel ||
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alu->op == nir_op_vec2 ||
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alu->op == nir_op_vec3 ||
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alu->op == nir_op_vec4 ||
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alu->op == nir_op_imov ||
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alu->op == nir_op_fmov ||
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alu_instr_is_comparison(alu) ||
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alu_instr_is_type_conversion(alu))
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continue;
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bool has_phi_src_from_prev_block = false;
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bool all_non_phi_exist_in_prev_block = true;
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bool is_prev_result_undef = true;
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bool is_prev_result_const = true;
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nir_ssa_def *prev_srcs[8]; // FINISHME: Array size?
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nir_ssa_def *continue_srcs[8]; // FINISHME: Array size?
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for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
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nir_instr *const src_instr = alu->src[i].src.ssa->parent_instr;
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/* If the source is a phi in the loop header block, then the
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* prev_srcs and continue_srcs will come from the different sources
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* of the phi.
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*/
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if (src_instr->type == nir_instr_type_phi &&
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src_instr->block == header_block) {
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nir_phi_instr *const phi = nir_instr_as_phi(src_instr);
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/* Only strictly need to NULL out the pointers when the assertions
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* (below) are compiled in. Debugging a NULL pointer deref in the
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* wild is easier than debugging a random pointer deref, so set
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* NULL unconditionally just to be safe.
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*/
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prev_srcs[i] = NULL;
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continue_srcs[i] = NULL;
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nir_foreach_phi_src(src_of_phi, phi) {
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if (src_of_phi->pred == prev_block) {
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if (src_of_phi->src.ssa->parent_instr->type !=
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nir_instr_type_ssa_undef) {
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is_prev_result_undef = false;
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}
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if (src_of_phi->src.ssa->parent_instr->type !=
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nir_instr_type_load_const) {
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is_prev_result_const = false;
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}
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prev_srcs[i] = src_of_phi->src.ssa;
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has_phi_src_from_prev_block = true;
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} else
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continue_srcs[i] = src_of_phi->src.ssa;
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}
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assert(prev_srcs[i] != NULL);
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assert(continue_srcs[i] != NULL);
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} else {
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/* If the source is not a phi (or a phi in a block other than the
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* loop header), then the value must exist in prev_block.
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*/
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if (!nir_block_dominates(src_instr->block, prev_block)) {
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all_non_phi_exist_in_prev_block = false;
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break;
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}
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prev_srcs[i] = alu->src[i].src.ssa;
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continue_srcs[i] = alu->src[i].src.ssa;
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}
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}
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if (has_phi_src_from_prev_block && all_non_phi_exist_in_prev_block &&
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(is_prev_result_undef || is_prev_result_const)) {
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nir_block *const continue_block = find_continue_block(loop);
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nir_ssa_def *prev_value;
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if (!is_prev_result_undef) {
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b->cursor = nir_after_block(prev_block);
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prev_value = clone_alu_and_replace_src_defs(b, alu, prev_srcs);
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} else {
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/* Since the undef used as the source of the original ALU
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* instruction may have different number of components or
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* bit size than the result of that instruction, a new
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* undef must be created.
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*/
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nir_ssa_undef_instr *undef =
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nir_ssa_undef_instr_create(b->shader,
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alu->dest.dest.ssa.num_components,
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alu->dest.dest.ssa.bit_size);
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nir_instr_insert_after_block(prev_block, &undef->instr);
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prev_value = &undef->def;
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}
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/* Make a copy of the original ALU instruction. Replace the sources
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* of the new instruction that read a phi with an undef source from
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* prev_block with the non-undef source of that phi.
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*
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* Insert the new instruction at the end of the continue block.
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*/
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b->cursor = nir_after_block(continue_block);
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nir_ssa_def *const alu_copy =
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clone_alu_and_replace_src_defs(b, alu, continue_srcs);
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/* Make a new phi node that selects a value from prev_block and the
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* result of the new instruction from continue_block.
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*/
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nir_phi_instr *const phi = nir_phi_instr_create(b->shader);
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nir_phi_src *phi_src;
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phi_src = ralloc(phi, nir_phi_src);
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phi_src->pred = prev_block;
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phi_src->src = nir_src_for_ssa(prev_value);
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exec_list_push_tail(&phi->srcs, &phi_src->node);
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phi_src = ralloc(phi, nir_phi_src);
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phi_src->pred = continue_block;
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phi_src->src = nir_src_for_ssa(alu_copy);
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exec_list_push_tail(&phi->srcs, &phi_src->node);
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nir_ssa_dest_init(&phi->instr, &phi->dest,
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alu_copy->num_components, alu_copy->bit_size, NULL);
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b->cursor = nir_after_phis(header_block);
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nir_builder_instr_insert(b, &phi->instr);
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/* Modify all readers of the original ALU instruction to read the
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* result of the phi.
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*/
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nir_foreach_use_safe(use_src, &alu->dest.dest.ssa) {
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nir_instr_rewrite_src(use_src->parent_instr,
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use_src,
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nir_src_for_ssa(&phi->dest.ssa));
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}
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nir_foreach_if_use_safe(use_src, &alu->dest.dest.ssa) {
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nir_if_rewrite_condition(use_src->parent_if,
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nir_src_for_ssa(&phi->dest.ssa));
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}
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/* Since the original ALU instruction no longer has any readers, just
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* remove it.
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*/
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nir_instr_remove_v(&alu->instr);
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ralloc_free(alu);
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progress = true;
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}
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}
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return progress;
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}
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static bool
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is_block_empty(nir_block *block)
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{
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@ -853,6 +1146,7 @@ opt_if_safe_cf_list(nir_builder *b, struct exec_list *cf_list)
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case nir_cf_node_loop: {
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nir_loop *loop = nir_cf_node_as_loop(cf_node);
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progress |= opt_if_safe_cf_list(b, &loop->body);
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progress |= opt_split_alu_of_phi(b, loop);
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break;
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}
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