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nir: rename nir_const_value fields to include bitsize information 

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
This commit is contained in:
Iago Toral Quiroga 2016-03-16 12:11:34 +01:00 committed by Samuel Iglesias Gonsálvez
parent 9076c4e289
commit 084b24f558
24 changed files with 130 additions and 130 deletions
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4
src/compiler/nir/nir.c
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@ -700,10 +700,10 @@ nir_deref_get_const_initializer_load(nir_shader *shader, nir_deref_var *deref)
case GLSL_TYPE_FLOAT: case GLSL_TYPE_FLOAT:
case GLSL_TYPE_INT: case GLSL_TYPE_INT:
case GLSL_TYPE_UINT: case GLSL_TYPE_UINT:
load->value.u[i] = constant->value.u[matrix_offset + i]; load->value.u32[i] = constant->value.u[matrix_offset + i];
break; break;
case GLSL_TYPE_BOOL: case GLSL_TYPE_BOOL:
load->value.u[i] = constant->value.b[matrix_offset + i] ? load->value.u32[i] = constant->value.b[matrix_offset + i] ?
NIR_TRUE : NIR_FALSE; NIR_TRUE : NIR_FALSE;
break; break;
default: default:

12
src/compiler/nir/nir.h
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@ -1209,12 +1209,12 @@ nir_tex_instr_src_index(nir_tex_instr *instr, nir_tex_src_type type)
typedef struct { typedef struct {
union { union {
float f[4]; float f32[4];
double d[4]; double f64[4];
int32_t i[4]; int32_t i32[4];
uint32_t u[4]; uint32_t u32[4];
int64_t l[4]; int64_t i64[4];
uint64_t ul[4]; uint64_t u64[4];
}; };
} nir_const_value; } nir_const_value;

20
src/compiler/nir/nir_builder.h
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@ -90,7 +90,7 @@ nir_imm_float(nir_builder *build, float x)
nir_const_value v; nir_const_value v;
memset(&v, 0, sizeof(v)); memset(&v, 0, sizeof(v));
v.f[0] = x; v.f32[0] = x;
return nir_build_imm(build, 1, v); return nir_build_imm(build, 1, v);
} }
@ -101,10 +101,10 @@ nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
nir_const_value v; nir_const_value v;
memset(&v, 0, sizeof(v)); memset(&v, 0, sizeof(v));
v.f[0] = x; v.f32[0] = x;
v.f[1] = y; v.f32[1] = y;
v.f[2] = z; v.f32[2] = z;
v.f[3] = w; v.f32[3] = w;
return nir_build_imm(build, 4, v); return nir_build_imm(build, 4, v);
} }
@ -115,7 +115,7 @@ nir_imm_int(nir_builder *build, int x)
nir_const_value v; nir_const_value v;
memset(&v, 0, sizeof(v)); memset(&v, 0, sizeof(v));
v.i[0] = x; v.i32[0] = x;
return nir_build_imm(build, 1, v); return nir_build_imm(build, 1, v);
} }
@ -126,10 +126,10 @@ nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
nir_const_value v; nir_const_value v;
memset(&v, 0, sizeof(v)); memset(&v, 0, sizeof(v));
v.i[0] = x; v.i32[0] = x;
v.i[1] = y; v.i32[1] = y;
v.i[2] = z; v.i32[2] = z;
v.i[3] = w; v.i32[3] = w;
return nir_build_imm(build, 4, v); return nir_build_imm(build, 4, v);
} }

22
src/compiler/nir/nir_constant_expressions.py
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@ -22,19 +22,19 @@ def type_add_size(type_, size):
def get_const_field(type_): def get_const_field(type_):
if type_ == "int32": if type_ == "int32":
return "i" return "i32"
if type_ == "uint32": if type_ == "uint32":
return "u" return "u32"
if type_ == "int64": if type_ == "int64":
return "l" return "i64"
if type_ == "uint64": if type_ == "uint64":
return "ul" return "u64"
if type_ == "bool32": if type_ == "bool32":
return "b" return "u32"
if type_ == "float32": if type_ == "float32":
return "f" return "f32"
if type_ == "float64": if type_ == "float64":
return "d" return "f64"
raise Exception(str(type_)) raise Exception(str(type_))
assert(0) assert(0)
@ -294,7 +294,7 @@ evaluate_${name}(unsigned num_components, unsigned bit_size,
struct ${input_types[j]}_vec src${j} = { struct ${input_types[j]}_vec src${j} = {
% for k in range(op.input_sizes[j]): % for k in range(op.input_sizes[j]):
% if input_types[j] == "bool32": % if input_types[j] == "bool32":
_src[${j}].u[${k}] != 0, _src[${j}].u32[${k}] != 0,
% else: % else:
_src[${j}].${get_const_field(input_types[j])}[${k}], _src[${j}].${get_const_field(input_types[j])}[${k}],
% endif % endif
@ -316,7 +316,7 @@ evaluate_${name}(unsigned num_components, unsigned bit_size,
## Avoid unused variable warnings ## Avoid unused variable warnings
<% continue %> <% continue %>
% elif input_types[j] == "bool32": % elif input_types[j] == "bool32":
bool src${j} = _src[${j}].u[_i] != 0; bool src${j} = _src[${j}].u32[_i] != 0;
% else: % else:
${input_types[j]}_t src${j} = ${input_types[j]}_t src${j} =
_src[${j}].${get_const_field(input_types[j])}[_i]; _src[${j}].${get_const_field(input_types[j])}[_i];
@ -337,7 +337,7 @@ evaluate_${name}(unsigned num_components, unsigned bit_size,
## value of dst. ## value of dst.
% if output_type == "bool32": % if output_type == "bool32":
## Sanitize the C value to a proper NIR bool ## Sanitize the C value to a proper NIR bool
_dst_val.u[_i] = dst ? NIR_TRUE : NIR_FALSE; _dst_val.u32[_i] = dst ? NIR_TRUE : NIR_FALSE;
% else: % else:
_dst_val.${get_const_field(output_type)}[_i] = dst; _dst_val.${get_const_field(output_type)}[_i] = dst;
% endif % endif
@ -364,7 +364,7 @@ evaluate_${name}(unsigned num_components, unsigned bit_size,
% for k in range(op.output_size): % for k in range(op.output_size):
% if output_type == "bool32": % if output_type == "bool32":
## Sanitize the C value to a proper NIR bool ## Sanitize the C value to a proper NIR bool
_dst_val.u[${k}] = dst.${"xyzw"[k]} ? NIR_TRUE : NIR_FALSE; _dst_val.u32[${k}] = dst.${"xyzw"[k]} ? NIR_TRUE : NIR_FALSE;
% else: % else:
_dst_val.${get_const_field(output_type)}[${k}] = dst.${"xyzw"[k]}; _dst_val.${get_const_field(output_type)}[${k}] = dst.${"xyzw"[k]};
% endif % endif

4
src/compiler/nir/nir_gs_count_vertices.c
View File

@ -77,13 +77,13 @@ nir_gs_count_vertices(const nir_shader *shader)
return -1; return -1;
if (count == -1) if (count == -1)
count = val->i[0]; count = val->i32[0];
/* We've found contradictory set_vertex_count intrinsics. /* We've found contradictory set_vertex_count intrinsics.
* This can happen if there are early-returns in main() and * This can happen if there are early-returns in main() and
* different paths emit different numbers of vertices. * different paths emit different numbers of vertices.
*/ */
if (count != val->i[0]) if (count != val->i32[0])
return -1; return -1;
} }
} }

8
src/compiler/nir/nir_instr_set.c
View File

@ -81,9 +81,9 @@ hash_load_const(uint32_t hash, const nir_load_const_instr *instr)
{ {
hash = HASH(hash, instr->def.num_components); hash = HASH(hash, instr->def.num_components);
hash = _mesa_fnv32_1a_accumulate_block(hash, instr->value.f, hash = _mesa_fnv32_1a_accumulate_block(hash, instr->value.f32,
instr->def.num_components instr->def.num_components
* sizeof(instr->value.f[0])); * sizeof(instr->value.f32[0]));
return hash; return hash;
} }
@ -322,8 +322,8 @@ nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2)
if (load1->def.num_components != load2->def.num_components) if (load1->def.num_components != load2->def.num_components)
return false; return false;
return memcmp(load1->value.f, load2->value.f, return memcmp(load1->value.f32, load2->value.f32,
load1->def.num_components * sizeof(*load2->value.f)) == 0; load1->def.num_components * sizeof(*load2->value.f32)) == 0;
} }
case nir_instr_type_phi: { case nir_instr_type_phi: {
nir_phi_instr *phi1 = nir_instr_as_phi(instr1); nir_phi_instr *phi1 = nir_instr_as_phi(instr1);

6
src/compiler/nir/nir_lower_atomics.c
View File

@ -75,7 +75,7 @@ lower_instr(nir_intrinsic_instr *instr,
state->shader_program->UniformStorage[uniform_loc].opaque[state->shader->stage].index); state->shader_program->UniformStorage[uniform_loc].opaque[state->shader->stage].index);
nir_load_const_instr *offset_const = nir_load_const_instr_create(mem_ctx, 1); nir_load_const_instr *offset_const = nir_load_const_instr_create(mem_ctx, 1);
offset_const->value.u[0] = instr->variables[0]->var->data.offset; offset_const->value.u32[0] = instr->variables[0]->var->data.offset;
nir_instr_insert_before(&instr->instr, &offset_const->instr); nir_instr_insert_before(&instr->instr, &offset_const->instr);
@ -90,13 +90,13 @@ lower_instr(nir_intrinsic_instr *instr,
unsigned child_array_elements = tail->child != NULL ? unsigned child_array_elements = tail->child != NULL ?
glsl_get_aoa_size(tail->type) : 1; glsl_get_aoa_size(tail->type) : 1;
offset_const->value.u[0] += deref_array->base_offset * offset_const->value.u32[0] += deref_array->base_offset *
child_array_elements * ATOMIC_COUNTER_SIZE; child_array_elements * ATOMIC_COUNTER_SIZE;
if (deref_array->deref_array_type == nir_deref_array_type_indirect) { if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
nir_load_const_instr *atomic_counter_size = nir_load_const_instr *atomic_counter_size =
nir_load_const_instr_create(mem_ctx, 1); nir_load_const_instr_create(mem_ctx, 1);
atomic_counter_size->value.u[0] = child_array_elements * ATOMIC_COUNTER_SIZE; atomic_counter_size->value.u32[0] = child_array_elements * ATOMIC_COUNTER_SIZE;
nir_instr_insert_before(&instr->instr, &atomic_counter_size->instr); nir_instr_insert_before(&instr->instr, &atomic_counter_size->instr);
nir_alu_instr *mul = nir_alu_instr_create(mem_ctx, nir_op_imul); nir_alu_instr *mul = nir_alu_instr_create(mem_ctx, nir_op_imul);

2
src/compiler/nir/nir_lower_load_const_to_scalar.c
View File

@ -49,7 +49,7 @@ lower_load_const_instr_scalar(nir_load_const_instr *lower)
nir_ssa_def *loads[4]; nir_ssa_def *loads[4];
for (unsigned i = 0; i < lower->def.num_components; i++) { for (unsigned i = 0; i < lower->def.num_components; i++) {
nir_load_const_instr *load_comp = nir_load_const_instr_create(b.shader, 1); nir_load_const_instr *load_comp = nir_load_const_instr_create(b.shader, 1);
load_comp->value.u[0] = lower->value.u[i]; load_comp->value.u32[0] = lower->value.u32[i];
nir_builder_instr_insert(&b, &load_comp->instr); nir_builder_instr_insert(&b, &load_comp->instr);
loads[i] = &load_comp->def; loads[i] = &load_comp->def;
} }

2
src/compiler/nir/nir_lower_locals_to_regs.c
View File

@ -161,7 +161,7 @@ get_deref_reg_src(nir_deref_var *deref, nir_instr *instr,
if (src.reg.indirect) { if (src.reg.indirect) {
nir_load_const_instr *load_const = nir_load_const_instr *load_const =
nir_load_const_instr_create(state->shader, 1); nir_load_const_instr_create(state->shader, 1);
load_const->value.u[0] = glsl_get_length(parent_type); load_const->value.u32[0] = glsl_get_length(parent_type);
nir_instr_insert_before(instr, &load_const->instr); nir_instr_insert_before(instr, &load_const->instr);
nir_alu_instr *mul = nir_alu_instr_create(state->shader, nir_op_imul); nir_alu_instr *mul = nir_alu_instr_create(state->shader, nir_op_imul);

6
src/compiler/nir/nir_lower_tex.c
View File

@ -223,13 +223,13 @@ get_zero_or_one(nir_builder *b, nir_alu_type type, uint8_t swizzle_val)
memset(&v, 0, sizeof(v)); memset(&v, 0, sizeof(v));
if (swizzle_val == 4) { if (swizzle_val == 4) {
v.u[0] = v.u[1] = v.u[2] = v.u[3] = 0; v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 0;
} else { } else {
assert(swizzle_val == 5); assert(swizzle_val == 5);
if (type == nir_type_float) if (type == nir_type_float)
v.f[0] = v.f[1] = v.f[2] = v.f[3] = 1.0; v.f32[0] = v.f32[1] = v.f32[2] = v.f32[3] = 1.0;
else else
v.u[0] = v.u[1] = v.u[2] = v.u[3] = 1; v.u32[0] = v.u32[1] = v.u32[2] = v.u32[3] = 1;
} }
return nir_build_imm(b, 4, v); return nir_build_imm(b, 4, v);

6
src/compiler/nir/nir_opt_constant_folding.c
View File

@ -77,9 +77,9 @@ constant_fold_alu_instr(nir_alu_instr *instr, void *mem_ctx)
for (unsigned j = 0; j < nir_ssa_alu_instr_src_components(instr, i); for (unsigned j = 0; j < nir_ssa_alu_instr_src_components(instr, i);
j++) { j++) {
if (load_const->def.bit_size == 64) if (load_const->def.bit_size == 64)
src[i].ul[j] = load_const->value.ul[instr->src[i].swizzle[j]]; src[i].u64[j] = load_const->value.u64[instr->src[i].swizzle[j]];
else else
src[i].u[j] = load_const->value.u[instr->src[i].swizzle[j]]; src[i].u32[j] = load_const->value.u32[instr->src[i].swizzle[j]];
} }
/* We shouldn't have any source modifiers in the optimization loop. */ /* We shouldn't have any source modifiers in the optimization loop. */
@ -131,7 +131,7 @@ constant_fold_deref(nir_instr *instr, nir_deref_var *deref)
nir_load_const_instr *indirect = nir_load_const_instr *indirect =
nir_instr_as_load_const(arr->indirect.ssa->parent_instr); nir_instr_as_load_const(arr->indirect.ssa->parent_instr);
arr->base_offset += indirect->value.u[0]; arr->base_offset += indirect->value.u32[0];
/* Clear out the source */ /* Clear out the source */
nir_instr_rewrite_src(instr, &arr->indirect, nir_src_for_ssa(NULL)); nir_instr_rewrite_src(instr, &arr->indirect, nir_src_for_ssa(NULL));

2
src/compiler/nir/nir_opt_dead_cf.c
View File

@ -228,7 +228,7 @@ dead_cf_block(nir_block *block)
if (!const_value) if (!const_value)
return false; return false;
opt_constant_if(following_if, const_value->u[0] != 0); opt_constant_if(following_if, const_value->u32[0] != 0);
return true; return true;
} }

2
src/compiler/nir/nir_print.c
View File

@ -711,7 +711,7 @@ print_load_const_instr(nir_load_const_instr *instr, print_state *state)
* and then print the float in a comment for readability. * and then print the float in a comment for readability.
*/ */
fprintf(fp, "0x%08x /* %f */", instr->value.u[i], instr->value.f[i]); fprintf(fp, "0x%08x /* %f */", instr->value.u32[i], instr->value.f32[i]);
} }
fprintf(fp, ")"); fprintf(fp, ")");

10
src/compiler/nir/nir_search.c
View File

@ -161,7 +161,7 @@ match_value(const nir_search_value *value, nir_alu_instr *instr, unsigned src,
switch (nir_op_infos[instr->op].input_types[src]) { switch (nir_op_infos[instr->op].input_types[src]) {
case nir_type_float: case nir_type_float:
for (unsigned i = 0; i < num_components; ++i) { for (unsigned i = 0; i < num_components; ++i) {
if (load->value.f[new_swizzle[i]] != const_val->data.f) if (load->value.f32[new_swizzle[i]] != const_val->data.f)
return false; return false;
} }
return true; return true;
@ -169,7 +169,7 @@ match_value(const nir_search_value *value, nir_alu_instr *instr, unsigned src,
case nir_type_uint: case nir_type_uint:
case nir_type_bool: case nir_type_bool:
for (unsigned i = 0; i < num_components; ++i) { for (unsigned i = 0; i < num_components; ++i) {
if (load->value.i[new_swizzle[i]] != const_val->data.i) if (load->value.i32[new_swizzle[i]] != const_val->data.i)
return false; return false;
} }
return true; return true;
@ -304,15 +304,15 @@ construct_value(const nir_search_value *value, nir_alu_type type,
switch (type) { switch (type) {
case nir_type_float: case nir_type_float:
load->def.name = ralloc_asprintf(mem_ctx, "%f", c->data.f); load->def.name = ralloc_asprintf(mem_ctx, "%f", c->data.f);
load->value.f[0] = c->data.f; load->value.f32[0] = c->data.f;
break; break;
case nir_type_int: case nir_type_int:
load->def.name = ralloc_asprintf(mem_ctx, "%d", c->data.i); load->def.name = ralloc_asprintf(mem_ctx, "%d", c->data.i);
load->value.i[0] = c->data.i; load->value.i32[0] = c->data.i;
break; break;
case nir_type_uint: case nir_type_uint:
case nir_type_bool: case nir_type_bool:
load->value.u[0] = c->data.u; load->value.u32[0] = c->data.u;
break; break;
default: default:
unreachable("Invalid alu source type"); unreachable("Invalid alu source type");

2
src/gallium/auxiliary/nir/tgsi_to_nir.c
View File

@ -459,7 +459,7 @@ ttn_emit_immediate(struct ttn_compile *c)
c->next_imm++; c->next_imm++;
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
load_const->value.u[i] = tgsi_imm->u[i].Uint; load_const->value.u32[i] = tgsi_imm->u[i].Uint;
nir_builder_instr_insert(b, &load_const->instr); nir_builder_instr_insert(b, &load_const->instr);
} }

10
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
View File

@ -1017,7 +1017,7 @@ emit_intrinsic_load_ubo(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
const_offset = nir_src_as_const_value(intr->src[1]); const_offset = nir_src_as_const_value(intr->src[1]);
if (const_offset) { if (const_offset) {
off += const_offset->u[0]; off += const_offset->u32[0];
} else { } else {
/* For load_ubo_indirect, second src is indirect offset: */ /* For load_ubo_indirect, second src is indirect offset: */
src1 = get_src(ctx, &intr->src[1])[0]; src1 = get_src(ctx, &intr->src[1])[0];
@ -1159,7 +1159,7 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
idx = nir_intrinsic_base(intr); idx = nir_intrinsic_base(intr);
const_offset = nir_src_as_const_value(intr->src[0]); const_offset = nir_src_as_const_value(intr->src[0]);
if (const_offset) { if (const_offset) {
idx += const_offset->u[0]; idx += const_offset->u32[0];
for (int i = 0; i < intr->num_components; i++) { for (int i = 0; i < intr->num_components; i++) {
unsigned n = idx * 4 + i; unsigned n = idx * 4 + i;
dst[i] = create_uniform(ctx, n); dst[i] = create_uniform(ctx, n);
@ -1186,7 +1186,7 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
idx = nir_intrinsic_base(intr); idx = nir_intrinsic_base(intr);
const_offset = nir_src_as_const_value(intr->src[0]); const_offset = nir_src_as_const_value(intr->src[0]);
if (const_offset) { if (const_offset) {
idx += const_offset->u[0]; idx += const_offset->u32[0];
for (int i = 0; i < intr->num_components; i++) { for (int i = 0; i < intr->num_components; i++) {
unsigned n = idx * 4 + i; unsigned n = idx * 4 + i;
dst[i] = ctx->ir->inputs[n]; dst[i] = ctx->ir->inputs[n];
@ -1213,7 +1213,7 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
idx = nir_intrinsic_base(intr); idx = nir_intrinsic_base(intr);
const_offset = nir_src_as_const_value(intr->src[1]); const_offset = nir_src_as_const_value(intr->src[1]);
compile_assert(ctx, const_offset != NULL); compile_assert(ctx, const_offset != NULL);
idx += const_offset->u[0]; idx += const_offset->u32[0];
src = get_src(ctx, &intr->src[0]); src = get_src(ctx, &intr->src[0]);
for (int i = 0; i < intr->num_components; i++) { for (int i = 0; i < intr->num_components; i++) {
@ -1301,7 +1301,7 @@ emit_load_const(struct ir3_compile *ctx, nir_load_const_instr *instr)
struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def, struct ir3_instruction **dst = get_dst_ssa(ctx, &instr->def,
instr->def.num_components); instr->def.num_components);
for (int i = 0; i < instr->def.num_components; i++) for (int i = 0; i < instr->def.num_components; i++)
dst[i] = create_immed(ctx->block, instr->value.u[i]); dst[i] = create_immed(ctx->block, instr->value.u32[i]);
} }
static void static void

6
src/gallium/drivers/vc4/vc4_nir_lower_io.c
View File

@ -183,7 +183,7 @@ vc4_nir_lower_vertex_attr(struct vc4_compile *c, nir_builder *b,
* with an offset value of 0. * with an offset value of 0.
*/ */
assert(nir_src_as_const_value(intr->src[0]) && assert(nir_src_as_const_value(intr->src[0]) &&
nir_src_as_const_value(intr->src[0])->u[0] == 0); nir_src_as_const_value(intr->src[0])->u32[0] == 0);
/* Generate dword loads for the VPM values (Since these intrinsics may /* Generate dword loads for the VPM values (Since these intrinsics may
* be reordered, the actual reads will be generated at the top of the * be reordered, the actual reads will be generated at the top of the
@ -256,7 +256,7 @@ vc4_nir_lower_fs_input(struct vc4_compile *c, nir_builder *b,
* with an offset value of 0. * with an offset value of 0.
*/ */
assert(nir_src_as_const_value(intr->src[0]) && assert(nir_src_as_const_value(intr->src[0]) &&
nir_src_as_const_value(intr->src[0])->u[0] == 0); nir_src_as_const_value(intr->src[0])->u32[0] == 0);
/* Generate scalar loads equivalent to the original VEC4. */ /* Generate scalar loads equivalent to the original VEC4. */
nir_ssa_def *dests[4]; nir_ssa_def *dests[4];
@ -339,7 +339,7 @@ vc4_nir_lower_output(struct vc4_compile *c, nir_builder *b,
* with an offset value of 0. * with an offset value of 0.
*/ */
assert(nir_src_as_const_value(intr->src[1]) && assert(nir_src_as_const_value(intr->src[1]) &&
nir_src_as_const_value(intr->src[1])->u[0] == 0); nir_src_as_const_value(intr->src[1])->u32[0] == 0);
b->cursor = nir_before_instr(&intr->instr); b->cursor = nir_before_instr(&intr->instr);

10
src/gallium/drivers/vc4/vc4_program.c
View File

@ -1521,7 +1521,7 @@ ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
{ {
struct qreg *qregs = ntq_init_ssa_def(c, &instr->def); struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
for (int i = 0; i < instr->def.num_components; i++) for (int i = 0; i < instr->def.num_components; i++)
qregs[i] = qir_uniform_ui(c, instr->value.u[i]); qregs[i] = qir_uniform_ui(c, instr->value.u32[i]);
_mesa_hash_table_insert(c->def_ht, &instr->def, qregs); _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
} }
@ -1555,7 +1555,7 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
assert(instr->num_components == 1); assert(instr->num_components == 1);
const_offset = nir_src_as_const_value(instr->src[0]); const_offset = nir_src_as_const_value(instr->src[0]);
if (const_offset) { if (const_offset) {
offset = instr->const_index[0] + const_offset->u[0]; offset = instr->const_index[0] + const_offset->u32[0];
assert(offset % 4 == 0); assert(offset % 4 == 0);
/* We need dwords */ /* We need dwords */
offset = offset / 4; offset = offset / 4;
@ -1586,7 +1586,7 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
const_offset = nir_src_as_const_value(instr->src[0]); const_offset = nir_src_as_const_value(instr->src[0]);
assert(const_offset && "vc4 doesn't support indirect inputs"); assert(const_offset && "vc4 doesn't support indirect inputs");
if (instr->const_index[0] >= VC4_NIR_TLB_COLOR_READ_INPUT) { if (instr->const_index[0] >= VC4_NIR_TLB_COLOR_READ_INPUT) {
assert(const_offset->u[0] == 0); assert(const_offset->u32[0] == 0);
/* Reads of the per-sample color need to be done in /* Reads of the per-sample color need to be done in
* order. * order.
*/ */
@ -1600,7 +1600,7 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
} }
*dest = c->color_reads[sample_index]; *dest = c->color_reads[sample_index];
} else { } else {
offset = instr->const_index[0] + const_offset->u[0]; offset = instr->const_index[0] + const_offset->u32[0];
*dest = c->inputs[offset]; *dest = c->inputs[offset];
} }
break; break;
@ -1608,7 +1608,7 @@ ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
case nir_intrinsic_store_output: case nir_intrinsic_store_output:
const_offset = nir_src_as_const_value(instr->src[1]); const_offset = nir_src_as_const_value(instr->src[1]);
assert(const_offset && "vc4 doesn't support indirect outputs"); assert(const_offset && "vc4 doesn't support indirect outputs");
offset = instr->const_index[0] + const_offset->u[0]; offset = instr->const_index[0] + const_offset->u32[0];
/* MSAA color outputs are the only case where we have an /* MSAA color outputs are the only case where we have an
* output that's not lowered to being a store of a single 32 * output that's not lowered to being a store of a single 32

70
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View File

@ -527,10 +527,10 @@ fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
enum opcode extract_op; enum opcode extract_op;
if (src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16) { if (src0->op == nir_op_extract_u16 || src0->op == nir_op_extract_i16) {
assert(element->u[0] <= 1); assert(element->u32[0] <= 1);
extract_op = SHADER_OPCODE_EXTRACT_WORD; extract_op = SHADER_OPCODE_EXTRACT_WORD;
} else { } else {
assert(element->u[0] <= 3); assert(element->u32[0] <= 3);
extract_op = SHADER_OPCODE_EXTRACT_BYTE; extract_op = SHADER_OPCODE_EXTRACT_BYTE;
} }
@ -539,7 +539,7 @@ fs_visitor::optimize_extract_to_float(nir_alu_instr *instr,
op0 = offset(op0, bld, src0->src[0].swizzle[0]); op0 = offset(op0, bld, src0->src[0].swizzle[0]);
set_saturate(instr->dest.saturate, set_saturate(instr->dest.saturate,
bld.emit(extract_op, result, op0, brw_imm_ud(element->u[0]))); bld.emit(extract_op, result, op0, brw_imm_ud(element->u32[0])));
return true; return true;
} }
@ -558,11 +558,11 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
return false; return false;
nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src); nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
if (!value1 || fabsf(value1->f[0]) != 1.0f) if (!value1 || fabsf(value1->f32[0]) != 1.0f)
return false; return false;
nir_const_value *value2 = nir_src_as_const_value(instr->src[2].src); nir_const_value *value2 = nir_src_as_const_value(instr->src[2].src);
if (!value2 || fabsf(value2->f[0]) != 1.0f) if (!value2 || fabsf(value2->f32[0]) != 1.0f)
return false; return false;
fs_reg tmp = vgrf(glsl_type::int_type); fs_reg tmp = vgrf(glsl_type::int_type);
@ -582,7 +582,7 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
* surely be TRIANGLES * surely be TRIANGLES
*/ */
if (value1->f[0] == -1.0f) { if (value1->f32[0] == -1.0f) {
g0.negate = true; g0.negate = true;
} }
@ -610,7 +610,7 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
* surely be TRIANGLES * surely be TRIANGLES
*/ */
if (value1->f[0] == -1.0f) { if (value1->f32[0] == -1.0f) {
g1_6.negate = true; g1_6.negate = true;
} }
@ -1115,7 +1115,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_extract_i8: { case nir_op_extract_i8: {
nir_const_value *byte = nir_src_as_const_value(instr->src[1].src); nir_const_value *byte = nir_src_as_const_value(instr->src[1].src);
bld.emit(SHADER_OPCODE_EXTRACT_BYTE, bld.emit(SHADER_OPCODE_EXTRACT_BYTE,
result, op[0], brw_imm_ud(byte->u[0])); result, op[0], brw_imm_ud(byte->u32[0]));
break; break;
} }
@ -1123,7 +1123,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_extract_i16: { case nir_op_extract_i16: {
nir_const_value *word = nir_src_as_const_value(instr->src[1].src); nir_const_value *word = nir_src_as_const_value(instr->src[1].src);
bld.emit(SHADER_OPCODE_EXTRACT_WORD, bld.emit(SHADER_OPCODE_EXTRACT_WORD,
result, op[0], brw_imm_ud(word->u[0])); result, op[0], brw_imm_ud(word->u32[0]));
break; break;
} }
@ -1150,7 +1150,7 @@ fs_visitor::nir_emit_load_const(const fs_builder &bld,
fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components); fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components);
for (unsigned i = 0; i < instr->def.num_components; i++) for (unsigned i = 0; i < instr->def.num_components; i++)
bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i[i])); bld.MOV(offset(reg, bld, i), brw_imm_d(instr->value.i32[i]));
nir_ssa_values[instr->def.index] = reg; nir_ssa_values[instr->def.index] = reg;
} }
@ -1686,9 +1686,9 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
const bool is_point_size = (base_offset == 0); const bool is_point_size = (base_offset == 0);
if (offset_const != NULL && vertex_const != NULL && if (offset_const != NULL && vertex_const != NULL &&
4 * (base_offset + offset_const->u[0]) < push_reg_count) { 4 * (base_offset + offset_const->u32[0]) < push_reg_count) {
int imm_offset = (base_offset + offset_const->u[0]) * 4 + int imm_offset = (base_offset + offset_const->u32[0]) * 4 +
vertex_const->u[0] * push_reg_count; vertex_const->u32[0] * push_reg_count;
/* This input was pushed into registers. */ /* This input was pushed into registers. */
if (is_point_size) { if (is_point_size) {
/* gl_PointSize comes in .w */ /* gl_PointSize comes in .w */
@ -1710,7 +1710,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
if (vertex_const) { if (vertex_const) {
/* The vertex index is constant; just select the proper URB handle. */ /* The vertex index is constant; just select the proper URB handle. */
icp_handle = icp_handle =
retype(brw_vec8_grf(first_icp_handle + vertex_const->i[0], 0), retype(brw_vec8_grf(first_icp_handle + vertex_const->i32[0], 0),
BRW_REGISTER_TYPE_UD); BRW_REGISTER_TYPE_UD);
} else { } else {
/* The vertex index is non-constant. We need to use indirect /* The vertex index is non-constant. We need to use indirect
@ -1754,7 +1754,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
if (offset_const) { if (offset_const) {
/* Constant indexing - use global offset. */ /* Constant indexing - use global offset. */
inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle); inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
inst->offset = base_offset + offset_const->u[0]; inst->offset = base_offset + offset_const->u32[0];
inst->base_mrf = -1; inst->base_mrf = -1;
inst->mlen = 1; inst->mlen = 1;
inst->regs_written = num_components; inst->regs_written = num_components;
@ -1792,7 +1792,7 @@ fs_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
* add_const_offset_to_base() will fold other constant offsets * add_const_offset_to_base() will fold other constant offsets
* into instr->const_index[0]. * into instr->const_index[0].
*/ */
assert(const_value->u[0] == 0); assert(const_value->u32[0] == 0);
return fs_reg(); return fs_reg();
} }
@ -2110,7 +2110,7 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]); nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]);
if (const_sample) { if (const_sample) {
unsigned msg_data = const_sample->i[0] << 4; unsigned msg_data = const_sample->i32[0] << 4;
emit_pixel_interpolater_send(bld, emit_pixel_interpolater_send(bld,
FS_OPCODE_INTERPOLATE_AT_SAMPLE, FS_OPCODE_INTERPOLATE_AT_SAMPLE,
@ -2177,8 +2177,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
if (const_offset) { if (const_offset) {
unsigned off_x = MIN2((int)(const_offset->f[0] * 16), 7) & 0xf; unsigned off_x = MIN2((int)(const_offset->f32[0] * 16), 7) & 0xf;
unsigned off_y = MIN2((int)(const_offset->f[1] * 16), 7) & 0xf; unsigned off_y = MIN2((int)(const_offset->f32[1] * 16), 7) & 0xf;
emit_pixel_interpolater_send(bld, emit_pixel_interpolater_send(bld,
FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
@ -2536,8 +2536,8 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
if (const_offset) { if (const_offset) {
/* Offsets are in bytes but they should always be multiples of 4 */ /* Offsets are in bytes but they should always be multiples of 4 */
assert(const_offset->u[0] % 4 == 0); assert(const_offset->u32[0] % 4 == 0);
src.reg_offset = const_offset->u[0] / 4; src.reg_offset = const_offset->u32[0] / 4;
} else { } else {
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0])); src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
} }
@ -2554,7 +2554,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
if (const_index) { if (const_index) {
const unsigned index = stage_prog_data->binding_table.ubo_start + const unsigned index = stage_prog_data->binding_table.ubo_start +
const_index->u[0]; const_index->u32[0];
surf_index = brw_imm_ud(index); surf_index = brw_imm_ud(index);
brw_mark_surface_used(prog_data, index); brw_mark_surface_used(prog_data, index);
} else { } else {
@ -2587,12 +2587,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg packed_consts = vgrf(glsl_type::float_type); fs_reg packed_consts = vgrf(glsl_type::float_type);
packed_consts.type = dest.type; packed_consts.type = dest.type;
struct brw_reg const_offset_reg = brw_imm_ud(const_offset->u[0] & ~15); struct brw_reg const_offset_reg = brw_imm_ud(const_offset->u32[0] & ~15);
bld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts, bld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts,
surf_index, const_offset_reg); surf_index, const_offset_reg);
for (unsigned i = 0; i < instr->num_components; i++) { for (unsigned i = 0; i < instr->num_components; i++) {
packed_consts.set_smear(const_offset->u[0] % 16 / 4 + i); packed_consts.set_smear(const_offset->u32[0] % 16 / 4 + i);
/* The std140 packing rules don't allow vectors to cross 16-byte /* The std140 packing rules don't allow vectors to cross 16-byte
* boundaries, and a reg is 32 bytes. * boundaries, and a reg is 32 bytes.
@ -2615,7 +2615,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg surf_index; fs_reg surf_index;
if (const_uniform_block) { if (const_uniform_block) {
unsigned index = stage_prog_data->binding_table.ssbo_start + unsigned index = stage_prog_data->binding_table.ssbo_start +
const_uniform_block->u[0]; const_uniform_block->u32[0];
surf_index = brw_imm_ud(index); surf_index = brw_imm_ud(index);
brw_mark_surface_used(prog_data, index); brw_mark_surface_used(prog_data, index);
} else { } else {
@ -2634,7 +2634,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg offset_reg; fs_reg offset_reg;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
if (const_offset) { if (const_offset) {
offset_reg = brw_imm_ud(const_offset->u[0]); offset_reg = brw_imm_ud(const_offset->u32[0]);
} else { } else {
offset_reg = get_nir_src(instr->src[1]); offset_reg = get_nir_src(instr->src[1]);
} }
@ -2660,7 +2660,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg offset_reg; fs_reg offset_reg;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
if (const_offset) { if (const_offset) {
offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u[0]); offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u32[0]);
} else { } else {
offset_reg = vgrf(glsl_type::uint_type); offset_reg = vgrf(glsl_type::uint_type);
bld.ADD(offset_reg, bld.ADD(offset_reg,
@ -2704,7 +2704,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
if (const_offset) { if (const_offset) {
offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u[0] + offset_reg = brw_imm_ud(instr->const_index[0] + const_offset->u32[0] +
4 * first_component); 4 * first_component);
} else { } else {
offset_reg = vgrf(glsl_type::uint_type); offset_reg = vgrf(glsl_type::uint_type);
@ -2738,7 +2738,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
assert(const_offset && "Indirect input loads not allowed"); assert(const_offset && "Indirect input loads not allowed");
src = offset(src, bld, const_offset->u[0]); src = offset(src, bld, const_offset->u32[0]);
for (unsigned j = 0; j < instr->num_components; j++) { for (unsigned j = 0; j < instr->num_components; j++) {
bld.MOV(offset(dest, bld, j), offset(src, bld, j)); bld.MOV(offset(dest, bld, j), offset(src, bld, j));
@ -2755,7 +2755,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
nir_src_as_const_value(instr->src[1]); nir_src_as_const_value(instr->src[1]);
if (const_uniform_block) { if (const_uniform_block) {
unsigned index = stage_prog_data->binding_table.ssbo_start + unsigned index = stage_prog_data->binding_table.ssbo_start +
const_uniform_block->u[0]; const_uniform_block->u32[0];
surf_index = brw_imm_ud(index); surf_index = brw_imm_ud(index);
brw_mark_surface_used(prog_data, index); brw_mark_surface_used(prog_data, index);
} else { } else {
@ -2786,7 +2786,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
fs_reg offset_reg; fs_reg offset_reg;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
if (const_offset) { if (const_offset) {
offset_reg = brw_imm_ud(const_offset->u[0] + 4 * first_component); offset_reg = brw_imm_ud(const_offset->u32[0] + 4 * first_component);
} else { } else {
offset_reg = vgrf(glsl_type::uint_type); offset_reg = vgrf(glsl_type::uint_type);
bld.ADD(offset_reg, bld.ADD(offset_reg,
@ -2814,7 +2814,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
assert(const_offset && "Indirect output stores not allowed"); assert(const_offset && "Indirect output stores not allowed");
new_dest = offset(new_dest, bld, const_offset->u[0]); new_dest = offset(new_dest, bld, const_offset->u32[0]);
for (unsigned j = 0; j < instr->num_components; j++) { for (unsigned j = 0; j < instr->num_components; j++) {
bld.MOV(offset(new_dest, bld, j), offset(src, bld, j)); bld.MOV(offset(new_dest, bld, j), offset(src, bld, j));
@ -2855,7 +2855,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
case nir_intrinsic_get_buffer_size: { case nir_intrinsic_get_buffer_size: {
nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]); nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]);
unsigned ssbo_index = const_uniform_block ? const_uniform_block->u[0] : 0; unsigned ssbo_index = const_uniform_block ? const_uniform_block->u32[0] : 0;
int reg_width = dispatch_width / 8; int reg_width = dispatch_width / 8;
/* Set LOD = 0 */ /* Set LOD = 0 */
@ -2906,7 +2906,7 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder &bld,
nir_const_value *const_surface = nir_src_as_const_value(instr->src[0]); nir_const_value *const_surface = nir_src_as_const_value(instr->src[0]);
if (const_surface) { if (const_surface) {
unsigned surf_index = stage_prog_data->binding_table.ssbo_start + unsigned surf_index = stage_prog_data->binding_table.ssbo_start +
const_surface->u[0]; const_surface->u32[0];
surface = brw_imm_ud(surf_index); surface = brw_imm_ud(surf_index);
brw_mark_surface_used(prog_data, surf_index); brw_mark_surface_used(prog_data, surf_index);
} else { } else {
@ -3031,7 +3031,7 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
nir_const_value *const_offset = nir_const_value *const_offset =
nir_src_as_const_value(instr->src[i].src); nir_src_as_const_value(instr->src[i].src);
if (const_offset) { if (const_offset) {
tex_offset = brw_imm_ud(brw_texture_offset(const_offset->i, 3)); tex_offset = brw_imm_ud(brw_texture_offset(const_offset->i32, 3));
} else { } else {
tex_offset = retype(src, BRW_REGISTER_TYPE_D); tex_offset = retype(src, BRW_REGISTER_TYPE_D);
} }

4
src/mesa/drivers/dri/i965/brw_nir.c
View File

@ -77,7 +77,7 @@ add_const_offset_to_base_block(nir_block *block, void *closure)
nir_const_value *const_offset = nir_src_as_const_value(*offset); nir_const_value *const_offset = nir_src_as_const_value(*offset);
if (const_offset) { if (const_offset) {
intrin->const_index[0] += const_offset->u[0]; intrin->const_index[0] += const_offset->u32[0];
b->cursor = nir_before_instr(&intrin->instr); b->cursor = nir_before_instr(&intrin->instr);
nir_instr_rewrite_src(&intrin->instr, offset, nir_instr_rewrite_src(&intrin->instr, offset,
nir_src_for_ssa(nir_imm_int(b, 0))); nir_src_for_ssa(nir_imm_int(b, 0)));
@ -175,7 +175,7 @@ remap_patch_urb_offsets(nir_block *block, void *closure)
if (vertex) { if (vertex) {
nir_const_value *const_vertex = nir_src_as_const_value(*vertex); nir_const_value *const_vertex = nir_src_as_const_value(*vertex);
if (const_vertex) { if (const_vertex) {
intrin->const_index[0] += const_vertex->u[0] * intrin->const_index[0] += const_vertex->u32[0] *
state->vue_map->num_per_vertex_slots; state->vue_map->num_per_vertex_slots;
} else { } else {
state->b.cursor = nir_before_instr(&intrin->instr); state->b.cursor = nir_before_instr(&intrin->instr);

2
src/mesa/drivers/dri/i965/brw_nir_analyze_boolean_resolves.c
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@ -225,7 +225,7 @@ analyze_boolean_resolves_block(nir_block *block, void *void_state)
* have to worry about resolving them. * have to worry about resolving them.
*/ */
instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK; instr->pass_flags &= ~BRW_NIR_BOOLEAN_MASK;
if (load->value.u[0] == NIR_TRUE || load->value.u[0] == NIR_FALSE) { if (load->value.u32[0] == NIR_TRUE || load->value.u32[0] == NIR_FALSE) {
instr->pass_flags |= BRW_NIR_BOOLEAN_NO_RESOLVE; instr->pass_flags |= BRW_NIR_BOOLEAN_NO_RESOLVE;
} else { } else {
instr->pass_flags |= BRW_NIR_NON_BOOLEAN; instr->pass_flags |= BRW_NIR_NON_BOOLEAN;

4
src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
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@ -70,8 +70,8 @@ vec4_gs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
/* Make up a type...we have no way of knowing... */ /* Make up a type...we have no way of knowing... */
const glsl_type *const type = glsl_type::ivec(instr->num_components); const glsl_type *const type = glsl_type::ivec(instr->num_components);
src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u[0] + src = src_reg(ATTR, BRW_VARYING_SLOT_COUNT * vertex->u32[0] +
instr->const_index[0] + offset->u[0], instr->const_index[0] + offset->u32[0],
type); type);
/* gl_PointSize is passed in the .w component of the VUE header */ /* gl_PointSize is passed in the .w component of the VUE header */
if (instr->const_index[0] == VARYING_SLOT_PSIZ) if (instr->const_index[0] == VARYING_SLOT_PSIZ)

44
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
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@ -352,7 +352,7 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
* add_const_offset_to_base() will fold other constant offsets * add_const_offset_to_base() will fold other constant offsets
* into instr->const_index[0]. * into instr->const_index[0].
*/ */
assert(const_value->u[0] == 0); assert(const_value->u32[0] == 0);
return src_reg(); return src_reg();
} }
@ -378,13 +378,13 @@ vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
continue; continue;
for (unsigned j = i; j < instr->def.num_components; j++) { for (unsigned j = i; j < instr->def.num_components; j++) {
if (instr->value.u[i] == instr->value.u[j]) { if (instr->value.u32[i] == instr->value.u32[j]) {
writemask |= 1 << j; writemask |= 1 << j;
} }
} }
reg.writemask = writemask; reg.writemask = writemask;
emit(MOV(reg, brw_imm_d(instr->value.i[i]))); emit(MOV(reg, brw_imm_d(instr->value.i32[i])));
remaining &= ~writemask; remaining &= ~writemask;
} }
@ -409,7 +409,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
/* We set EmitNoIndirectInput for VS */ /* We set EmitNoIndirectInput for VS */
assert(const_offset); assert(const_offset);
src = src_reg(ATTR, instr->const_index[0] + const_offset->u[0], src = src_reg(ATTR, instr->const_index[0] + const_offset->u32[0],
glsl_type::uvec4_type); glsl_type::uvec4_type);
dest = get_nir_dest(instr->dest, src.type); dest = get_nir_dest(instr->dest, src.type);
@ -423,7 +423,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
assert(const_offset); assert(const_offset);
int varying = instr->const_index[0] + const_offset->u[0]; int varying = instr->const_index[0] + const_offset->u32[0];
src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F, src = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_F,
instr->num_components); instr->num_components);
@ -434,7 +434,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
case nir_intrinsic_get_buffer_size: { case nir_intrinsic_get_buffer_size: {
nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]); nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]);
unsigned ssbo_index = const_uniform_block ? const_uniform_block->u[0] : 0; unsigned ssbo_index = const_uniform_block ? const_uniform_block->u32[0] : 0;
const unsigned index = const unsigned index =
prog_data->base.binding_table.ssbo_start + ssbo_index; prog_data->base.binding_table.ssbo_start + ssbo_index;
@ -467,7 +467,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
nir_src_as_const_value(instr->src[1]); nir_src_as_const_value(instr->src[1]);
if (const_uniform_block) { if (const_uniform_block) {
unsigned index = prog_data->base.binding_table.ssbo_start + unsigned index = prog_data->base.binding_table.ssbo_start +
const_uniform_block->u[0]; const_uniform_block->u32[0];
surf_index = brw_imm_ud(index); surf_index = brw_imm_ud(index);
brw_mark_surface_used(&prog_data->base, index); brw_mark_surface_used(&prog_data->base, index);
} else { } else {
@ -485,7 +485,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
src_reg offset_reg; src_reg offset_reg;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
if (const_offset) { if (const_offset) {
offset_reg = brw_imm_ud(const_offset->u[0]); offset_reg = brw_imm_ud(const_offset->u32[0]);
} else { } else {
offset_reg = get_nir_src(instr->src[2], 1); offset_reg = get_nir_src(instr->src[2], 1);
} }
@ -605,7 +605,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
src_reg surf_index; src_reg surf_index;
if (const_uniform_block) { if (const_uniform_block) {
unsigned index = prog_data->base.binding_table.ssbo_start + unsigned index = prog_data->base.binding_table.ssbo_start +
const_uniform_block->u[0]; const_uniform_block->u32[0];
surf_index = brw_imm_ud(index); surf_index = brw_imm_ud(index);
brw_mark_surface_used(&prog_data->base, index); brw_mark_surface_used(&prog_data->base, index);
@ -626,7 +626,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
src_reg offset_reg; src_reg offset_reg;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
if (const_offset) { if (const_offset) {
offset_reg = brw_imm_ud(const_offset->u[0]); offset_reg = brw_imm_ud(const_offset->u32[0]);
} else { } else {
offset_reg = get_nir_src(instr->src[1], 1); offset_reg = get_nir_src(instr->src[1], 1);
} }
@ -706,8 +706,8 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
if (const_offset) { if (const_offset) {
/* Offsets are in bytes but they should always be multiples of 16 */ /* Offsets are in bytes but they should always be multiples of 16 */
assert(const_offset->u[0] % 16 == 0); assert(const_offset->u32[0] % 16 == 0);
src.reg_offset = const_offset->u[0] / 16; src.reg_offset = const_offset->u32[0] / 16;
} else { } else {
src_reg tmp = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_D, 1); src_reg tmp = get_nir_src(instr->src[0], BRW_REGISTER_TYPE_D, 1);
src.reladdr = new(mem_ctx) src_reg(tmp); src.reladdr = new(mem_ctx) src_reg(tmp);
@ -767,7 +767,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
* as an immediate. * as an immediate.
*/ */
const unsigned index = prog_data->base.binding_table.ubo_start + const unsigned index = prog_data->base.binding_table.ubo_start +
const_block_index->u[0]; const_block_index->u32[0];
surf_index = brw_imm_ud(index); surf_index = brw_imm_ud(index);
brw_mark_surface_used(&prog_data->base, index); brw_mark_surface_used(&prog_data->base, index);
} else { } else {
@ -792,7 +792,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
src_reg offset; src_reg offset;
nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]); nir_const_value *const_offset = nir_src_as_const_value(instr->src[1]);
if (const_offset) { if (const_offset) {
offset = brw_imm_ud(const_offset->u[0] & ~15); offset = brw_imm_ud(const_offset->u32[0] & ~15);
} else { } else {
offset = get_nir_src(instr->src[1], nir_type_int, 1); offset = get_nir_src(instr->src[1], nir_type_int, 1);
} }
@ -807,10 +807,10 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
packed_consts.swizzle = brw_swizzle_for_size(instr->num_components); packed_consts.swizzle = brw_swizzle_for_size(instr->num_components);
if (const_offset) { if (const_offset) {
packed_consts.swizzle += BRW_SWIZZLE4(const_offset->u[0] % 16 / 4, packed_consts.swizzle += BRW_SWIZZLE4(const_offset->u32[0] % 16 / 4,
const_offset->u[0] % 16 / 4, const_offset->u32[0] % 16 / 4,
const_offset->u[0] % 16 / 4, const_offset->u32[0] % 16 / 4,
const_offset->u[0] % 16 / 4); const_offset->u32[0] % 16 / 4);
} }
emit(MOV(dest, packed_consts)); emit(MOV(dest, packed_consts));
@ -852,7 +852,7 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr)
nir_const_value *const_surface = nir_src_as_const_value(instr->src[0]); nir_const_value *const_surface = nir_src_as_const_value(instr->src[0]);
if (const_surface) { if (const_surface) {
unsigned surf_index = prog_data->base.binding_table.ssbo_start + unsigned surf_index = prog_data->base.binding_table.ssbo_start +
const_surface->u[0]; const_surface->u32[0];
surface = brw_imm_ud(surf_index); surface = brw_imm_ud(surf_index);
brw_mark_surface_used(&prog_data->base, surf_index); brw_mark_surface_used(&prog_data->base, surf_index);
} else { } else {
@ -1049,12 +1049,12 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
* operand. If we can determine that one of the args is in the low * operand. If we can determine that one of the args is in the low
* 16 bits, though, we can just emit a single MUL. * 16 bits, though, we can just emit a single MUL.
*/ */
if (value0 && value0->u[0] < (1 << 16)) { if (value0 && value0->u32[0] < (1 << 16)) {
if (devinfo->gen < 7) if (devinfo->gen < 7)
emit(MUL(dst, op[0], op[1])); emit(MUL(dst, op[0], op[1]));
else else
emit(MUL(dst, op[1], op[0])); emit(MUL(dst, op[1], op[0]));
} else if (value1 && value1->u[0] < (1 << 16)) { } else if (value1 && value1->u32[0] < (1 << 16)) {
if (devinfo->gen < 7) if (devinfo->gen < 7)
emit(MUL(dst, op[1], op[0])); emit(MUL(dst, op[1], op[0]));
else else
@ -1725,7 +1725,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
nir_const_value *const_offset = nir_const_value *const_offset =
nir_src_as_const_value(instr->src[i].src); nir_src_as_const_value(instr->src[i].src);
if (const_offset) { if (const_offset) {
constant_offset = brw_texture_offset(const_offset->i, 3); constant_offset = brw_texture_offset(const_offset->i32, 3);
} else { } else {
offset_value = offset_value =
get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2); get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2);

2
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
View File

@ -355,7 +355,7 @@ vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]); nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]);
src_reg vertex_index = src_reg vertex_index =
vertex_const ? src_reg(brw_imm_ud(vertex_const->u[0])) vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0]))
: get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1); : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1);
dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D);