radeonsi: implement sdma for GFX9
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
parent
4cacba0c86
commit
082d1c1686
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@ -106,6 +106,186 @@ static unsigned encode_tile_info(struct si_context *sctx,
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(G_009910_PIPE_CONFIG(tile_mode) << 26);
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}
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static bool si_sdma_v4_copy_texture(struct si_context *sctx,
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struct pipe_resource *dst,
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unsigned dst_level,
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unsigned dstx, unsigned dsty, unsigned dstz,
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struct pipe_resource *src,
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unsigned src_level,
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const struct pipe_box *src_box)
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{
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struct si_texture *ssrc = (struct si_texture*)src;
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struct si_texture *sdst = (struct si_texture*)dst;
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unsigned bpp = sdst->surface.bpe;
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uint64_t dst_address = sdst->buffer.gpu_address +
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sdst->surface.u.gfx9.surf_offset;
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uint64_t src_address = ssrc->buffer.gpu_address +
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ssrc->surface.u.gfx9.surf_offset;
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unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch;
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unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch;
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uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.gfx9.surf_slice_size) / bpp;
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uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.gfx9.surf_slice_size) / bpp;
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unsigned srcx = src_box->x / ssrc->surface.blk_w;
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unsigned srcy = src_box->y / ssrc->surface.blk_h;
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unsigned srcz = src_box->z;
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unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
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unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
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unsigned copy_depth = src_box->depth;
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unsigned xalign = MAX2(1, 4 / bpp);
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assert(src_level <= src->last_level);
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assert(dst_level <= dst->last_level);
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assert(sdst->surface.u.gfx9.surf_offset +
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dst_slice_pitch * bpp * (dstz + src_box->depth) <=
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sdst->buffer.buf->size);
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assert(ssrc->surface.u.gfx9.surf_offset +
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src_slice_pitch * bpp * (srcz + src_box->depth) <=
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ssrc->buffer.buf->size);
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if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
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dstz, ssrc, src_level, src_box))
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return false;
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dstx /= sdst->surface.blk_w;
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dsty /= sdst->surface.blk_h;
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if (srcx >= (1 << 14) ||
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srcy >= (1 << 14) ||
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srcz >= (1 << 11) ||
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dstx >= (1 << 14) ||
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dsty >= (1 << 14) ||
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dstz >= (1 << 11))
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return false;
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/* Linear -> linear sub-window copy. */
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if (ssrc->surface.is_linear &&
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sdst->surface.is_linear) {
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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/* Check if everything fits into the bitfields */
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if (!(src_pitch <= (1 << 19) &&
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dst_pitch <= (1 << 19) &&
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src_slice_pitch <= (1 << 28) &&
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dst_slice_pitch <= (1 << 28) &&
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copy_width <= (1 << 14) &&
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copy_height <= (1 << 14) &&
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copy_depth <= (1 << 11)))
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return false;
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si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
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src_address += ssrc->surface.u.gfx9.offset[src_level];
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dst_address += sdst->surface.u.gfx9.offset[dst_level];
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/* Check alignments */
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if ((src_address % 4) != 0 ||
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(dst_address % 4) != 0 ||
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(src_pitch % xalign) != 0)
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return false;
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
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(util_logbase2(bpp) << 29));
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radeon_emit(cs, src_address);
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radeon_emit(cs, src_address >> 32);
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radeon_emit(cs, srcx | (srcy << 16));
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radeon_emit(cs, srcz | ((src_pitch - 1) << 13));
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radeon_emit(cs, src_slice_pitch - 1);
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radeon_emit(cs, dst_address);
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radeon_emit(cs, dst_address >> 32);
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radeon_emit(cs, dstx | (dsty << 16));
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radeon_emit(cs, dstz | ((dst_pitch - 1) << 13));
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radeon_emit(cs, dst_slice_pitch - 1);
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radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
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radeon_emit(cs, (copy_depth - 1));
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return true;
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}
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/* Linear <-> Tiled sub-window copy */
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if (ssrc->surface.is_linear != sdst->surface.is_linear) {
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struct si_texture *tiled = ssrc->surface.is_linear ? sdst : ssrc;
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struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
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unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
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unsigned linear_level = linear == ssrc ? src_level : dst_level;
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unsigned tiled_x = tiled == ssrc ? srcx : dstx;
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unsigned linear_x = linear == ssrc ? srcx : dstx;
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unsigned tiled_y = tiled == ssrc ? srcy : dsty;
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unsigned linear_y = linear == ssrc ? srcy : dsty;
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unsigned tiled_z = tiled == ssrc ? srcz : dstz;
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unsigned linear_z = linear == ssrc ? srcz : dstz;
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unsigned tiled_width = tiled == ssrc ?
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DIV_ROUND_UP(ssrc->buffer.b.b.width0, ssrc->surface.blk_w) :
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DIV_ROUND_UP(sdst->buffer.b.b.width0, sdst->surface.blk_w);
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unsigned tiled_height = tiled == ssrc ?
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DIV_ROUND_UP(ssrc->buffer.b.b.height0, ssrc->surface.blk_h) :
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DIV_ROUND_UP(sdst->buffer.b.b.height0, sdst->surface.blk_h);
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unsigned tiled_depth = tiled == ssrc ?
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ssrc->buffer.b.b.depth0 :
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sdst->buffer.b.b.depth0;
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unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
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unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
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uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
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uint64_t linear_address = linear == ssrc ? src_address : dst_address;
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struct radeon_cmdbuf *cs = sctx->dma_cs;
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linear_address += linear->surface.u.gfx9.offset[linear_level];
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/* Check if everything fits into the bitfields */
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if (!(tiled_x <= (1 << 14) &&
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tiled_y <= (1 << 14) &&
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tiled_z <= (1 << 11) &&
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tiled_width <= (1 << 14) &&
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tiled_height <= (1 << 14) &&
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tiled_depth <= (1 << 11) &&
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tiled->surface.u.gfx9.surf.epitch <= (1 << 16) &&
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linear_x <= (1 << 14) &&
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linear_y <= (1 << 14) &&
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linear_z <= (1 << 11) &&
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linear_pitch <= (1 << 14) &&
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linear_slice_pitch <= (1 << 28) &&
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copy_width <= (1 << 14) &&
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copy_height <= (1 << 14) &&
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copy_depth <= (1 << 11)))
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return false;
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/* Check alignments */
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if ((tiled_address % 256 != 0) ||
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(linear_address % 4 != 0) ||
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(linear_pitch % xalign != 0) ||
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(linear_slice_pitch % xalign != 0))
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return false;
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si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
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radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
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CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
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tiled->buffer.b.b.last_level << 20 |
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tiled_level << 24 |
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(linear == sdst ? 1u : 0) << 31);
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radeon_emit(cs, (uint32_t) tiled_address);
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radeon_emit(cs, (uint32_t) (tiled_address >> 32));
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radeon_emit(cs, tiled_x | (tiled_y << 16));
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radeon_emit(cs, tiled_z | ((tiled_width - 1) << 16));
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radeon_emit(cs, (tiled_height - 1) | (tiled_depth - 1) << 16);
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radeon_emit(cs, util_logbase2(bpp) |
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tiled->surface.u.gfx9.surf.swizzle_mode << 3 |
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tiled->surface.u.gfx9.resource_type << 9 |
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tiled->surface.u.gfx9.surf.epitch << 16);
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radeon_emit(cs, (uint32_t) linear_address);
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radeon_emit(cs, (uint32_t) (linear_address >> 32));
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radeon_emit(cs, linear_x | (linear_y << 16));
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radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
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radeon_emit(cs, linear_slice_pitch - 1);
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radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
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radeon_emit(cs, (copy_depth - 1));
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return true;
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}
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return false;
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}
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static bool cik_sdma_copy_texture(struct si_context *sctx,
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struct pipe_resource *dst,
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unsigned dst_level,
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@ -517,12 +697,17 @@ static void cik_sdma_copy(struct pipe_context *ctx,
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*
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* Keep SDMA enabled on APUs.
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*/
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if ((sctx->screen->debug_flags & DBG(FORCE_DMA) ||
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!sctx->screen->info.has_dedicated_vram) &&
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(sctx->chip_class == GFX7 || sctx->chip_class == GFX8) &&
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cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
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src, src_level, src_box))
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return;
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if (sctx->screen->debug_flags & DBG(FORCE_DMA) ||
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!sctx->screen->info.has_dedicated_vram) {
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if ((sctx->chip_class == GFX7 || sctx->chip_class == GFX8) &&
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cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
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src, src_level, src_box))
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return;
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else if (sctx->chip_class == GFX9 &&
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si_sdma_v4_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
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src, src_level, src_box))
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return;
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}
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fallback:
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si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
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