i965/fs: Add an exec_size field to fs_inst
This will, eventually, allow us to manage execution sizes of instructions in a much more natural way from the fs_visitor level. i965/fs: Explicitly set instruction execute size a couple of places i965/blorp: Explicitly set instruction execute sizes Since blorp is all 16-wide and nothing isn't, in general, very careful about register width, we'll just set it all explicitly. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand
parent
fbc0a798ee
commit
071ac3a467
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@ -96,7 +96,7 @@ brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
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unsigned msg_length,
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bool use_header)
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{
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fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE);
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fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE, 16);
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inst->src[0] = src0;
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inst->base_mrf = msg_reg_nr;
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@ -65,7 +65,7 @@ protected:
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{
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emit_cmp(op, x, y);
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fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
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fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 16, dst, src);
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mv->predicate = BRW_PREDICATE_NORMAL;
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insts.push_tail(mv);
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}
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@ -82,17 +82,17 @@ protected:
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const struct brw_reg &src3)
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{
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insts.push_tail(
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new (mem_ctx) fs_inst(BRW_OPCODE_LRP, dst, src1, src2, src3));
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new (mem_ctx) fs_inst(BRW_OPCODE_LRP, 16, dst, src1, src2, src3));
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}
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inline void emit_mov(const struct brw_reg& dst, const struct brw_reg& src)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 16, dst, src));
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}
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inline void emit_mov_8(const struct brw_reg& dst, const struct brw_reg& src)
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{
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fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, dst, src);
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fs_inst *mv = new (mem_ctx) fs_inst(BRW_OPCODE_MOV, 8, dst, src);
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mv->force_uncompressed = true;
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insts.push_tail(mv);
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}
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@ -101,21 +101,21 @@ protected:
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AND, dst, src1, src2));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_AND, 16, dst, src1, src2));
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}
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inline void emit_add(const struct brw_reg& dst,
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ADD, 16, dst, src1, src2));
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}
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inline void emit_add_8(const struct brw_reg& dst,
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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fs_inst *add = new (mem_ctx) fs_inst(BRW_OPCODE_ADD, dst, src1, src2);
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fs_inst *add = new (mem_ctx) fs_inst(BRW_OPCODE_ADD, 8, dst, src1, src2);
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add->force_uncompressed = true;
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insts.push_tail(add);
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}
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@ -124,40 +124,40 @@ protected:
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MUL, dst, src1, src2));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_MUL, 16, dst, src1, src2));
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}
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inline void emit_shr(const struct brw_reg& dst,
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHR, dst, src1, src2));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHR, 16, dst, src1, src2));
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}
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inline void emit_shl(const struct brw_reg& dst,
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHL, dst, src1, src2));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_SHL, 16, dst, src1, src2));
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}
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inline void emit_or(const struct brw_reg& dst,
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const struct brw_reg& src1,
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const struct brw_reg& src2)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_OR, dst, src1, src2));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_OR, 16, dst, src1, src2));
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}
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inline void emit_frc(const struct brw_reg& dst,
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const struct brw_reg& src)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_FRC, dst, src));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_FRC, 16, dst, src));
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}
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inline void emit_rndd(const struct brw_reg& dst,
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const struct brw_reg& src)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, dst, src));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_RNDD, 16, dst, src));
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}
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inline void emit_cmp_if(enum brw_conditional_mod op,
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@ -165,17 +165,17 @@ protected:
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const struct brw_reg &y)
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{
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emit_cmp(op, x, y);
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_IF));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_IF, 16));
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}
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inline void emit_else(void)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ELSE));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ELSE, 16));
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}
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inline void emit_endif(void)
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{
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ENDIF));
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insts.push_tail(new (mem_ctx) fs_inst(BRW_OPCODE_ENDIF, 16));
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}
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private:
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@ -53,7 +53,8 @@ extern "C" {
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#include "glsl/glsl_types.h"
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void
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fs_inst::init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources)
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fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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fs_reg *src, int sources)
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{
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memset(this, 0, sizeof(*this));
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@ -61,6 +62,33 @@ fs_inst::init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources)
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this->dst = dst;
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this->src = src;
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this->sources = sources;
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this->exec_size = exec_size;
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assert(dst.file != IMM && dst.file != UNIFORM);
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/* If exec_size == 0, try to guess it from the registers. Since all
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* manner of things may use hardware registers, we first try to guess
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* based on GRF registers. If this fails, we will go ahead and take the
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* width from the destination register.
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*/
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if (this->exec_size == 0) {
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if (dst.file == GRF) {
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this->exec_size = dst.width;
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} else {
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for (int i = 0; i < sources; ++i) {
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if (src[i].file != GRF)
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continue;
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if (this->exec_size <= 1)
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this->exec_size = src[i].width;
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assert(src[i].width == 1 || src[i].width == this->exec_size);
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}
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}
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if (this->exec_size == 0 && dst.file != BAD_FILE)
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this->exec_size = dst.width;
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}
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assert(this->exec_size != 0);
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this->conditional_mod = BRW_CONDITIONAL_NONE;
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@ -84,17 +112,46 @@ fs_inst::init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources)
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this->writes_accumulator = false;
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}
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fs_inst::fs_inst()
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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init(BRW_OPCODE_NOP, 8, dst, src, 0);
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}
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fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size)
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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init(opcode, exec_size, reg_undef, src, 0);
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}
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fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst)
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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init(opcode, dst, src, 0);
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init(opcode, 0, dst, src, 0);
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}
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fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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const fs_reg &src0)
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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src[0] = src0;
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init(opcode, exec_size, dst, src, 1);
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}
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fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0)
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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src[0] = src0;
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init(opcode, dst, src, 1);
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init(opcode, 0, dst, src, 1);
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}
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fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1)
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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src[0] = src0;
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src[1] = src1;
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init(opcode, exec_size, dst, src, 2);
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}
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fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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@ -103,7 +160,17 @@ fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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src[0] = src0;
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src[1] = src1;
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init(opcode, dst, src, 2);
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init(opcode, 0, dst, src, 2);
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}
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fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1, const fs_reg &src2)
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{
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fs_reg *src = ralloc_array(this, fs_reg, 3);
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src[0] = src0;
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src[1] = src1;
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src[2] = src2;
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init(opcode, exec_size, dst, src, 3);
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}
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fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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@ -113,12 +180,18 @@ fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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src[0] = src0;
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src[1] = src1;
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src[2] = src2;
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init(opcode, dst, src, 3);
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init(opcode, 0, dst, src, 3);
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}
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fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources)
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{
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init(opcode, dst, src, sources);
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init(opcode, 0, dst, src, sources);
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}
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fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
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fs_reg src[], int sources)
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{
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init(opcode, exec_width, dst, src, sources);
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}
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fs_inst::fs_inst(const fs_inst &that)
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@ -206,7 +279,7 @@ ALU2(MAC)
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fs_inst *
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fs_visitor::IF(enum brw_predicate predicate)
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{
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF);
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width);
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inst->predicate = predicate;
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return inst;
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}
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@ -217,7 +290,7 @@ fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
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enum brw_conditional_mod condition)
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{
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assert(brw->gen == 6);
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
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fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width,
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reg_null_d, src0, src1);
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inst->conditional_mod = condition;
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return inst;
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@ -358,6 +431,7 @@ fs_visitor::DEP_RESOLVE_MOV(int grf)
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/* The caller always wants uncompressed to emit the minimal extra
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* dependencies, and to avoid having to deal with aligning its regs to 2.
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*/
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inst->exec_size = 8;
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inst->force_uncompressed = true;
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return inst;
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@ -380,6 +454,7 @@ fs_inst::equals(fs_inst *inst) const
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eot == inst->eot &&
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header_present == inst->header_present &&
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shadow_compare == inst->shadow_compare &&
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exec_size == inst->exec_size &&
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offset == inst->offset);
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}
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@ -605,6 +680,7 @@ fs_visitor::get_timestamp()
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*/
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mov->force_writemask_all = true;
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mov->force_uncompressed = true;
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mov->exec_size = 8;
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/* The caller wants the low 32 bits of the timestamp. Since it's running
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* at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
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@ -760,7 +836,7 @@ fs_visitor::no16(const char *format, ...)
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fs_inst *
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fs_visitor::emit(enum opcode opcode)
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{
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return emit(new(mem_ctx) fs_inst(opcode));
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return emit(new(mem_ctx) fs_inst(opcode, dispatch_width));
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}
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fs_inst *
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@ -2129,7 +2205,7 @@ fs_visitor::demote_pull_constants()
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} else {
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fs_reg offset = fs_reg((unsigned)(pull_index * 4) & ~15);
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fs_inst *pull =
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new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
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new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 8,
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dst, surf_index, offset);
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inst->insert_before(block, pull);
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inst->src[i].set_smear(pull_index & 3);
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@ -2840,7 +2916,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
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* by live variable analysis, or register allocation will explode.
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*/
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fs_inst *setup = new(mem_ctx) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET,
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payload, const_offset_reg);
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8, payload, const_offset_reg);
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setup->force_writemask_all = true;
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setup->ir = inst->ir;
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@ -193,18 +193,29 @@ public:
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class fs_inst : public backend_instruction {
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fs_inst &operator=(const fs_inst &);
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void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
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fs_reg *src, int sources);
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public:
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DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
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void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
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fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
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fs_inst();
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fs_inst(enum opcode opcode, uint8_t exec_size);
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fs_inst(enum opcode opcode, const fs_reg &dst);
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fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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const fs_reg &src0);
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fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
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fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1);
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fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1);
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fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
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fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
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const fs_reg &src1, const fs_reg &src2);
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fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
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fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
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fs_reg src[], int sources);
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fs_inst(const fs_inst &that);
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void resize_sources(uint8_t num_sources);
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@ -224,6 +235,13 @@ public:
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uint8_t sources; /**< Number of fs_reg sources. */
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/**
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* Execution size of the instruction. This is used by the generator to
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* generate the correct binary for the given fs_inst. Current valid
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* values are 1, 8, 16.
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*/
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uint8_t exec_size;
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/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
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* mod and predication.
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*/
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@ -944,7 +944,7 @@ fs_visitor::visit(ir_expression *ir)
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packed_consts.type = result.type;
|
||||
|
||||
fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
|
||||
emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
|
||||
emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 8,
|
||||
packed_consts, surf_index, const_offset_reg));
|
||||
|
||||
for (int i = 0; i < ir->type->vector_elements; i++) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue