etnaviv: fix two-sided stencil
* Set missing STENCIL_CONFIG_EXT2 bits * Swap stencil sides when rendering CCW Fixes following deqp tests (which were 99% failing): dEQP-GLES2.functional.fragment_ops.depth_stencil.* Note: deqp tests require --deqp-gl-config-name=rgba8888d24s8ms0 Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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@ -214,6 +214,8 @@ void
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etna_emit_state(struct etna_context *ctx)
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{
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struct etna_cmd_stream *stream = ctx->stream;
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unsigned ccw = ctx->rasterizer->front_ccw;
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/* Pre-reserve the command buffer space which we are likely to need.
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* This must cover all the state emitted below, and the following
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@ -466,13 +468,14 @@ etna_emit_state(struct etna_context *ctx)
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/*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE);
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}
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if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
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uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP;
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if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
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uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw];
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/*01418*/ EMIT_STATE(PE_STENCIL_OP, val);
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}
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if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF))) {
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uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG;
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/*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG);
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if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) {
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uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw];
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/*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG[ccw]);
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}
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if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
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uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP;
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@ -511,8 +514,8 @@ etna_emit_state(struct etna_context *ctx)
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abort();
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}
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}
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if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF))) {
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/*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT);
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if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) {
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/*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[ccw]);
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}
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if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
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struct etna_blend_state *blend = etna_blend_state(ctx->blend);
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@ -528,6 +531,9 @@ etna_emit_state(struct etna_context *ctx)
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/*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.PE_ALPHA_COLOR_EXT0);
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/*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.PE_ALPHA_COLOR_EXT1);
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}
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if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
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/*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]);
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}
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if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && ctx->specs.halti >= 3)
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/*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG);
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if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) {
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@ -152,8 +152,8 @@ struct compiled_blend_color {
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/* Compiled pipe_stencil_ref */
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struct compiled_stencil_ref {
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uint32_t PE_STENCIL_CONFIG;
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uint32_t PE_STENCIL_CONFIG_EXT;
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uint32_t PE_STENCIL_CONFIG[2];
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uint32_t PE_STENCIL_CONFIG_EXT[2];
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};
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/* Compiled pipe_scissor_state */
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@ -52,10 +52,12 @@ etna_set_stencil_ref(struct pipe_context *pctx, const struct pipe_stencil_ref *s
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ctx->stencil_ref_s = *sr;
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cs->PE_STENCIL_CONFIG = VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[0]);
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/* rest of bits weaved in from depth_stencil_alpha */
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cs->PE_STENCIL_CONFIG_EXT =
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VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[0]);
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for (unsigned i = 0; i < 2; i++) {
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cs->PE_STENCIL_CONFIG[i] =
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VIVS_PE_STENCIL_CONFIG_REF_FRONT(sr->ref_value[i]);
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cs->PE_STENCIL_CONFIG_EXT[i] =
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VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(sr->ref_value[!i]);
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}
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ctx->dirty |= ETNA_DIRTY_STENCIL_REF;
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}
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@ -104,21 +104,25 @@ etna_zsa_state_create(struct pipe_context *pctx,
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COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
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VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha.func) |
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VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(so->alpha.ref_value));
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cs->PE_STENCIL_OP =
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VIVS_PE_STENCIL_OP_FUNC_FRONT(so->stencil[0].func) |
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VIVS_PE_STENCIL_OP_FUNC_BACK(so->stencil[1].func) |
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VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so->stencil[0].fail_op)) |
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VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so->stencil[1].fail_op)) |
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VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so->stencil[0].zfail_op)) |
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VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so->stencil[1].zfail_op)) |
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VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so->stencil[0].zpass_op)) |
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VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so->stencil[1].zpass_op));
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cs->PE_STENCIL_CONFIG =
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translate_stencil_mode(so->stencil[0].enabled, so->stencil[1].enabled) |
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VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so->stencil[0].valuemask) |
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VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[0].writemask);
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/* XXX back masks in VIVS_PE_DEPTH_CONFIG_EXT? */
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/* XXX VIVS_PE_STENCIL_CONFIG_REF_FRONT comes from pipe_stencil_ref */
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for (unsigned i = 0; i < 2; i++) {
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cs->PE_STENCIL_OP[i] =
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VIVS_PE_STENCIL_OP_FUNC_FRONT(so->stencil[i].func) |
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VIVS_PE_STENCIL_OP_FUNC_BACK(so->stencil[!i].func) |
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VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(so->stencil[i].fail_op)) |
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VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(so->stencil[!i].fail_op)) |
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VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(so->stencil[i].zfail_op)) |
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VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(so->stencil[!i].zfail_op)) |
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VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(so->stencil[i].zpass_op)) |
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VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(so->stencil[!i].zpass_op));
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cs->PE_STENCIL_CONFIG[i] =
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translate_stencil_mode(so->stencil[i].enabled, so->stencil[!i].enabled) |
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VIVS_PE_STENCIL_CONFIG_MASK_FRONT(so->stencil[i].valuemask) |
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VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(so->stencil[i].writemask);
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cs->PE_STENCIL_CONFIG_EXT2[i] =
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VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(so->stencil[!i].valuemask) |
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VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(so->stencil[!i].writemask);
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}
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/* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
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return cs;
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@ -35,8 +35,10 @@ struct etna_zsa_state {
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uint32_t PE_DEPTH_CONFIG;
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uint32_t PE_ALPHA_OP;
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uint32_t PE_STENCIL_OP;
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uint32_t PE_STENCIL_CONFIG;
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uint32_t PE_STENCIL_OP[2];
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uint32_t PE_STENCIL_CONFIG[2];
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uint32_t PE_STENCIL_CONFIG_EXT2[2];
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};
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static inline struct etna_zsa_state *
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