radv: Refactor cs_domain to be a winsys function.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10198>
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9de05fd36b
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057ec395a4
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@ -461,15 +461,6 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
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return cmd_buffer->record_result;
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return cmd_buffer->record_result;
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}
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}
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enum radeon_bo_domain
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radv_cmdbuffer_domain(const struct radeon_info *info, uint32_t perftest)
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{
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bool use_sam =
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(info->all_vram_visible && info->has_dedicated_vram && !(perftest & RADV_PERFTEST_NO_SAM)) ||
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(perftest & RADV_PERFTEST_SAM);
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return use_sam ? RADEON_DOMAIN_VRAM : RADEON_DOMAIN_GTT;
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}
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static bool
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static bool
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radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer, uint64_t min_needed)
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radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer, uint64_t min_needed)
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{
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{
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@ -481,11 +472,9 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer, uint64_t m
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new_size = MAX2(min_needed, 16 * 1024);
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new_size = MAX2(min_needed, 16 * 1024);
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new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
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new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
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bo = device->ws->buffer_create(
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bo = device->ws->buffer_create(device->ws, new_size, 4096, device->ws->cs_domain(device->ws),
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device->ws, new_size, 4096,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
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radv_cmdbuffer_domain(&device->physical_device->rad_info, device->instance->perftest_flags),
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RADEON_FLAG_32BIT | RADEON_FLAG_GTT_WC,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_32BIT |
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RADEON_FLAG_GTT_WC,
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RADV_BO_PRIORITY_UPLOAD_BUFFER);
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RADV_BO_PRIORITY_UPLOAD_BUFFER);
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if (!bo) {
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if (!bo) {
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@ -260,6 +260,8 @@ struct radeon_winsys {
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bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, int ring_index);
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bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, int ring_index);
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enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
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struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum ring_type ring_type);
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struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum ring_type ring_type);
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void (*cs_destroy)(struct radeon_cmdbuf *cs);
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void (*cs_destroy)(struct radeon_cmdbuf *cs);
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@ -338,6 +340,4 @@ radv_cs_add_buffer(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct ra
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ws->cs_add_buffer(cs, bo);
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ws->cs_add_buffer(cs, bo);
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}
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}
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enum radeon_bo_domain radv_cmdbuffer_domain(const struct radeon_info *info, uint32_t perftest);
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#endif /* RADV_RADEON_WINSYS_H */
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#endif /* RADV_RADEON_WINSYS_H */
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@ -620,11 +620,10 @@ cik_create_gfx_config(struct radv_device *device)
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radeon_emit(cs, PKT3_NOP_PAD);
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radeon_emit(cs, PKT3_NOP_PAD);
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}
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}
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device->gfx_init = device->ws->buffer_create(
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device->gfx_init =
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device->ws, cs->cdw * 4, 4096,
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device->ws->buffer_create(device->ws, cs->cdw * 4, 4096, device->ws->cs_domain(device->ws),
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radv_cmdbuffer_domain(&device->physical_device->rad_info, device->instance->perftest_flags),
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY |
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RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
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RADEON_FLAG_GTT_WC,
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RADV_BO_PRIORITY_CS);
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RADV_BO_PRIORITY_CS);
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if (!device->gfx_init)
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if (!device->gfx_init)
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goto fail;
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goto fail;
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@ -33,6 +33,8 @@
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#include "ac_debug.h"
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#include "ac_debug.h"
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#include "radv_amdgpu_bo.h"
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#include "radv_amdgpu_bo.h"
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#include "radv_amdgpu_cs.h"
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#include "radv_amdgpu_cs.h"
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#include "radv_amdgpu_winsys.h"
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#include "radv_debug.h"
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#include "radv_radeon_winsys.h"
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#include "radv_radeon_winsys.h"
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#include "sid.h"
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#include "sid.h"
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@ -175,6 +177,17 @@ radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs, enum ring_type ring_type)
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cs->hw_ip = ring_to_hw_ip(ring_type);
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cs->hw_ip = ring_to_hw_ip(ring_type);
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}
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}
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static enum radeon_bo_domain
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radv_amdgpu_cs_domain(const struct radeon_winsys *_ws)
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{
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const struct radv_amdgpu_winsys *ws = (const struct radv_amdgpu_winsys *)_ws;
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bool use_sam = (ws->info.all_vram_visible && ws->info.has_dedicated_vram &&
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!(ws->perftest & RADV_PERFTEST_NO_SAM)) ||
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(ws->perftest & RADV_PERFTEST_SAM);
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return use_sam ? RADEON_DOMAIN_VRAM : RADEON_DOMAIN_GTT;
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}
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static struct radeon_cmdbuf *
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static struct radeon_cmdbuf *
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radv_amdgpu_cs_create(struct radeon_winsys *ws, enum ring_type ring_type)
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radv_amdgpu_cs_create(struct radeon_winsys *ws, enum ring_type ring_type)
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{
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{
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@ -189,7 +202,7 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws, enum ring_type ring_type)
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if (cs->ws->use_ib_bos) {
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if (cs->ws->use_ib_bos) {
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cs->ib_buffer =
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cs->ib_buffer =
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ws->buffer_create(ws, ib_size, 0, cs->ws->cs_bo_domain,
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ws->buffer_create(ws, ib_size, 0, radv_amdgpu_cs_domain(ws),
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
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RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
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RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
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RADV_BO_PRIORITY_CS);
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RADV_BO_PRIORITY_CS);
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@ -309,7 +322,7 @@ radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
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cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
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cs->old_ib_buffers[cs->num_old_ib_buffers++] = cs->ib_buffer;
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cs->ib_buffer =
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cs->ib_buffer =
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cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0, cs->ws->cs_bo_domain,
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cs->ws->base.buffer_create(&cs->ws->base, ib_size, 0, radv_amdgpu_cs_domain(&cs->ws->base),
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
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RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
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RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
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RADV_BO_PRIORITY_CS);
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RADV_BO_PRIORITY_CS);
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@ -934,7 +947,7 @@ radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, int queue_id
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}
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}
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bos[j] = ws->buffer_create(
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bos[j] = ws->buffer_create(
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ws, 4 * size, 4096, aws->cs_bo_domain,
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ws, 4 * size, 4096, radv_amdgpu_cs_domain(ws),
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY,
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RADV_BO_PRIORITY_CS);
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RADV_BO_PRIORITY_CS);
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ptr = ws->buffer_map(bos[j]);
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ptr = ws->buffer_map(bos[j]);
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@ -976,7 +989,7 @@ radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, int queue_id
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assert(cnt);
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assert(cnt);
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bos[0] = ws->buffer_create(
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bos[0] = ws->buffer_create(
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ws, 4 * size, 4096, aws->cs_bo_domain,
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ws, 4 * size, 4096, radv_amdgpu_cs_domain(ws),
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY,
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY,
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RADV_BO_PRIORITY_CS);
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RADV_BO_PRIORITY_CS);
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ptr = ws->buffer_map(bos[0]);
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ptr = ws->buffer_map(bos[0]);
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@ -1650,6 +1663,7 @@ radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
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ws->base.ctx_create = radv_amdgpu_ctx_create;
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ws->base.ctx_create = radv_amdgpu_ctx_create;
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ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
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ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
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ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
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ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
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ws->base.cs_domain = radv_amdgpu_cs_domain;
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ws->base.cs_create = radv_amdgpu_cs_create;
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ws->base.cs_create = radv_amdgpu_cs_create;
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ws->base.cs_destroy = radv_amdgpu_cs_destroy;
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ws->base.cs_destroy = radv_amdgpu_cs_destroy;
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ws->base.cs_grow = radv_amdgpu_cs_grow;
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ws->base.cs_grow = radv_amdgpu_cs_grow;
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@ -235,10 +235,10 @@ radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags)
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if (debug_flags & RADV_DEBUG_NO_IBS)
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if (debug_flags & RADV_DEBUG_NO_IBS)
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ws->use_ib_bos = false;
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ws->use_ib_bos = false;
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ws->perftest = perftest_flags;
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ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
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ws->use_local_bos = perftest_flags & RADV_PERFTEST_LOCAL_BOS;
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ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
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ws->zero_all_vram_allocs = debug_flags & RADV_DEBUG_ZERO_VRAM;
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ws->use_llvm = debug_flags & RADV_DEBUG_LLVM;
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ws->use_llvm = debug_flags & RADV_DEBUG_LLVM;
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ws->cs_bo_domain = radv_cmdbuffer_domain(&ws->info, perftest_flags);
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u_rwlock_init(&ws->global_bo_list.lock);
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u_rwlock_init(&ws->global_bo_list.lock);
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list_inithead(&ws->log_bo_list);
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list_inithead(&ws->log_bo_list);
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u_rwlock_init(&ws->log_bo_list_lock);
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u_rwlock_init(&ws->log_bo_list_lock);
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@ -46,10 +46,10 @@ struct radv_amdgpu_winsys {
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bool debug_all_bos;
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bool debug_all_bos;
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bool debug_log_bos;
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bool debug_log_bos;
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bool use_ib_bos;
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bool use_ib_bos;
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enum radeon_bo_domain cs_bo_domain;
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bool zero_all_vram_allocs;
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bool zero_all_vram_allocs;
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bool use_local_bos;
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bool use_local_bos;
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bool use_llvm;
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bool use_llvm;
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uint64_t perftest;
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uint64_t allocated_vram;
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uint64_t allocated_vram;
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uint64_t allocated_vram_vis;
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uint64_t allocated_vram_vis;
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@ -59,6 +59,12 @@ radv_null_ctx_destroy(struct radeon_winsys_ctx *rwctx)
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FREE(ctx);
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FREE(ctx);
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}
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}
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static enum radeon_bo_domain
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radv_null_cs_domain(const struct radeon_winsys *_ws)
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{
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return RADEON_DOMAIN_GTT;
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}
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static struct radeon_cmdbuf *
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static struct radeon_cmdbuf *
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radv_null_cs_create(struct radeon_winsys *ws, enum ring_type ring_type)
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radv_null_cs_create(struct radeon_winsys *ws, enum ring_type ring_type)
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{
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{
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@ -97,6 +103,7 @@ radv_null_cs_init_functions(struct radv_null_winsys *ws)
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{
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{
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ws->base.ctx_create = radv_null_ctx_create;
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ws->base.ctx_create = radv_null_ctx_create;
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ws->base.ctx_destroy = radv_null_ctx_destroy;
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ws->base.ctx_destroy = radv_null_ctx_destroy;
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ws->base.cs_domain = radv_null_cs_domain;
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ws->base.cs_create = radv_null_cs_create;
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ws->base.cs_create = radv_null_cs_create;
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ws->base.cs_finalize = radv_null_cs_finalize;
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ws->base.cs_finalize = radv_null_cs_finalize;
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ws->base.cs_destroy = radv_null_cs_destroy;
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ws->base.cs_destroy = radv_null_cs_destroy;
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