radeonsi: implement TGSI opcodes TEX_LZ and TXF_LZ
This massively decreases VGPR spilling for DiRT Showdown, because we no longer have to use v4i32 for 2D fetches when level == 0. We now use v2i32 for those cases. DiRT Showdown - Spilled VGPRs: -26 (-81%) This surprisingly doesn't have any useful effect on performance (+ 0.05%).
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@ -416,6 +416,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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return 1;
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case PIPE_CAP_INT64:
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@ -482,7 +483,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_TGSI_FS_FBFETCH:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_UMA:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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return 0;
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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@ -4383,7 +4383,9 @@ static void tex_fetch_args(
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coords[3] = bld_base->base.one;
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/* Pack offsets. */
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if (has_offset && opcode != TGSI_OPCODE_TXF) {
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if (has_offset &&
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opcode != TGSI_OPCODE_TXF &&
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opcode != TGSI_OPCODE_TXF_LZ) {
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/* The offsets are six-bit signed integers packed like this:
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* X=[5:0], Y=[13:8], and Z=[21:16].
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*/
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@ -4541,8 +4543,8 @@ static void tex_fetch_args(
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memcpy(txf_address, address, sizeof(txf_address));
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/* Read FMASK using TXF. */
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inst.Instruction.Opcode = TGSI_OPCODE_TXF;
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/* Read FMASK using TXF_LZ. */
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inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
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inst.Texture.Texture = target;
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txf_emit_data.inst = &inst;
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txf_emit_data.chan = 0;
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@ -4593,7 +4595,8 @@ static void tex_fetch_args(
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final_sample, address[sample_chan], "");
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}
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if (opcode == TGSI_OPCODE_TXF) {
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if (opcode == TGSI_OPCODE_TXF ||
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opcode == TGSI_OPCODE_TXF_LZ) {
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/* add tex offsets */
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if (inst->Texture.NumOffsets) {
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struct lp_build_context *uint_bld = &bld_base->uint_bld;
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@ -4755,7 +4758,9 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
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switch (opcode) {
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case TGSI_OPCODE_TXF:
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args.opcode = target == TGSI_TEXTURE_2D_MSAA ||
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case TGSI_OPCODE_TXF_LZ:
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args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
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target == TGSI_TEXTURE_2D_MSAA ||
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target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
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ac_image_load : ac_image_load_mip;
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args.compare = false;
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@ -4772,6 +4777,9 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
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if (ctx->type != PIPE_SHADER_FRAGMENT)
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args.level_zero = true;
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break;
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case TGSI_OPCODE_TEX_LZ:
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args.level_zero = true;
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break;
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case TGSI_OPCODE_TXB:
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case TGSI_OPCODE_TXB2:
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assert(ctx->type == PIPE_SHADER_FRAGMENT);
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@ -6426,11 +6434,13 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
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bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
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bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
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bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
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