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radeonsi: implement TGSI opcodes TEX_LZ and TXF_LZ 

This massively decreases VGPR spilling for DiRT Showdown, because we
no longer have to use v4i32 for 2D fetches when level == 0.
We now use v2i32 for those cases.

DiRT Showdown - Spilled VGPRs: -26 (-81%)

This surprisingly doesn't have any useful effect on performance (+ 0.05%).
This commit is contained in:
Marek Olšák 2017-03-07 02:19:47 +01:00
parent a7cc9b0fcf
commit 0550f3d631
2 changed files with 16 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -416,6 +416,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
case PIPE_CAP_DOUBLES:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
return 1;
case PIPE_CAP_INT64:
@ -482,7 +483,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_UMA:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
return 0;
case PIPE_CAP_QUERY_BUFFER_OBJECT:

20
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -4383,7 +4383,9 @@ static void tex_fetch_args(
coords[3] = bld_base->base.one;
/* Pack offsets. */
if (has_offset && opcode != TGSI_OPCODE_TXF) {
if (has_offset &&
opcode != TGSI_OPCODE_TXF &&
opcode != TGSI_OPCODE_TXF_LZ) {
/* The offsets are six-bit signed integers packed like this:
* X=[5:0], Y=[13:8], and Z=[21:16].
*/
@ -4541,8 +4543,8 @@ static void tex_fetch_args(
memcpy(txf_address, address, sizeof(txf_address));
/* Read FMASK using TXF. */
inst.Instruction.Opcode = TGSI_OPCODE_TXF;
/* Read FMASK using TXF_LZ. */
inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
inst.Texture.Texture = target;
txf_emit_data.inst = &inst;
txf_emit_data.chan = 0;
@ -4593,7 +4595,8 @@ static void tex_fetch_args(
final_sample, address[sample_chan], "");
}
if (opcode == TGSI_OPCODE_TXF) {
if (opcode == TGSI_OPCODE_TXF ||
opcode == TGSI_OPCODE_TXF_LZ) {
/* add tex offsets */
if (inst->Texture.NumOffsets) {
struct lp_build_context *uint_bld = &bld_base->uint_bld;
@ -4755,7 +4758,9 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
switch (opcode) {
case TGSI_OPCODE_TXF:
args.opcode = target == TGSI_TEXTURE_2D_MSAA ||
case TGSI_OPCODE_TXF_LZ:
args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
ac_image_load : ac_image_load_mip;
args.compare = false;
@ -4772,6 +4777,9 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
if (ctx->type != PIPE_SHADER_FRAGMENT)
args.level_zero = true;
break;
case TGSI_OPCODE_TEX_LZ:
args.level_zero = true;
break;
case TGSI_OPCODE_TXB:
case TGSI_OPCODE_TXB2:
assert(ctx->type == PIPE_SHADER_FRAGMENT);
@ -6426,11 +6434,13 @@ static void si_init_shader_ctx(struct si_shader_context *ctx,
bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;