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nir: Define shifts according to SM5 specification. 

SPIR-V shifts are undefined for values >= bitsize, but SM5 shifts
are defined to only use the least significant bits.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Daniel Schürmann 2019-02-14 08:19:09 +01:00 committed by Jason Ekstrand
parent c4fb6b0c81
commit 0525bdc225
1 changed files with 6 additions and 4 deletions
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10
src/compiler/nir/nir_opcodes.py
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@ -610,10 +610,12 @@ binop("sge", tfloat, "", "(src0 >= src1) ? 1.0f : 0.0f") # Set on Greater or Equ
binop("seq", tfloat32, commutative, "(src0 == src1) ? 1.0f : 0.0f") # Set on Equal
binop("sne", tfloat32, commutative, "(src0 != src1) ? 1.0f : 0.0f") # Set on Not Equal
opcode("ishl", 0, tint, [0, 0], [tint, tuint32], "", "src0 << src1")
opcode("ishr", 0, tint, [0, 0], [tint, tuint32], "", "src0 >> src1")
opcode("ushr", 0, tuint, [0, 0], [tuint, tuint32], "", "src0 >> src1")
# SPIRV shifts are undefined for shift-operands >= bitsize,
# but SM5 shifts are defined to use the least significant bits, only
# The NIR definition is according to the SM5 specification.
opcode("ishl", 0, tint, [0, 0], [tint, tuint32], "", "src0 << (src1 & (sizeof(src0) * 8 - 1))")
opcode("ishr", 0, tint, [0, 0], [tint, tuint32], "", "src0 >> (src1 & (sizeof(src0) * 8 - 1))")
opcode("ushr", 0, tuint, [0, 0], [tuint, tuint32], "", "src0 >> (src1 & (sizeof(src0) * 8 - 1))")
# bitwise logic operators
#