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i965: perf: make revision variable available 

This will be used in the next commit to build up register programming.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Lionel Landwerlin 2017-07-25 17:17:48 +01:00
parent ca63a5ed3e
commit 05231a4e74
5 changed files with 10 additions and 8 deletions
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1
src/mesa/drivers/dri/i965/brw_context.h
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@ -1087,6 +1087,7 @@ struct brw_context
uint64_t subslice_mask; /** $SubsliceMask */
uint64_t gt_min_freq; /** $GpuMinFrequency */
uint64_t gt_max_freq; /** $GpuMaxFrequency */
uint64_t revision; /** $SkuRevisionId */
} sys_vars;
/* OA metric sets, indexed by GUID, as know by Mesa at build time,

1
src/mesa/drivers/dri/i965/brw_oa.py
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@ -175,6 +175,7 @@ hw_vars["$SubsliceMask"] = "brw->perfquery.sys_vars.subslice_mask"
hw_vars["$GpuTimestampFrequency"] = "brw->perfquery.sys_vars.timestamp_frequency"
hw_vars["$GpuMinFrequency"] = "brw->perfquery.sys_vars.gt_min_freq"
hw_vars["$GpuMaxFrequency"] = "brw->perfquery.sys_vars.gt_max_freq"
hw_vars["$SkuRevisionId"] = "brw->perfquery.sys_vars.revision"
def output_rpn_equation_code(set, counter, equation, counter_vars):
c("/* RPN equation: " + equation + " */")

4
src/mesa/drivers/dri/i965/brw_performance_query.c
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@ -1812,6 +1812,7 @@ init_oa_sys_vars(struct brw_context *brw, const char *sysfs_dev_dir)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
uint64_t min_freq_mhz = 0, max_freq_mhz = 0;
__DRIscreen *screen = brw->screen->driScrnPriv;
if (!read_sysfs_drm_device_file_uint64(brw, sysfs_dev_dir,
"gt_min_freq_mhz",
@ -1826,6 +1827,8 @@ init_oa_sys_vars(struct brw_context *brw, const char *sysfs_dev_dir)
brw->perfquery.sys_vars.gt_min_freq = min_freq_mhz * 1000000;
brw->perfquery.sys_vars.gt_max_freq = max_freq_mhz * 1000000;
brw->perfquery.sys_vars.timestamp_frequency = devinfo->timestamp_frequency;
brw->perfquery.sys_vars.revision = intel_device_get_revision(screen->fd);
brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices;
/* Assuming uniform distribution of subslices per slices. */
brw->perfquery.sys_vars.n_eu_sub_slices = devinfo->num_subslices[0];
@ -1848,7 +1851,6 @@ init_oa_sys_vars(struct brw_context *brw, const char *sysfs_dev_dir)
} else
unreachable("not reached");
} else {
__DRIscreen *screen = brw->screen->driScrnPriv;
drm_i915_getparam_t gp;
int ret;
int slice_mask = 0;

9
src/mesa/drivers/dri/i965/intel_screen.c
View File

@ -2129,14 +2129,9 @@ set_max_gl_versions(struct intel_screen *screen)
/**
* Return the revision (generally the revid field of the PCI header) of the
* graphics device.
*
* XXX: This function is useful to keep around even if it is not currently in
* use. It is necessary for new platforms and revision specific workarounds or
* features. Please don't remove it so that we know it at least continues to
* build.
*/
static __attribute__((__unused__)) int
brw_get_revision(int fd)
int
intel_device_get_revision(int fd)
{
struct drm_i915_getparam gp;
int revision;

3
src/mesa/drivers/dri/i965/intel_screen.h
View File

@ -136,6 +136,9 @@ double get_time(void);
const int*
intel_supported_msaa_modes(const struct intel_screen *screen);
int
intel_device_get_revision(int fd);
static inline bool
can_do_pipelined_register_writes(const struct intel_screen *screen)
{