intel: Rename WA_### to Wa_###
Commands used to do the changes: export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965" grep -E "WA_[[:digit:]]{10}" -rIl $SEARCH_PATH | xargs sed -ie "s/WA_\([[:digit:]]\{10\}\)/Wa_\1/g" Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
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@ -758,7 +758,7 @@ iris_emit_l3_config(struct iris_batch *batch,
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reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0;
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reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0;
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#endif
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#endif
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#if GFX_VER == 11
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#if GFX_VER == 11
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/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
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/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be set
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* in L3CNTLREG register. The default setting of the bit is not the
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* in L3CNTLREG register. The default setting of the bit is not the
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* desirable behavior.
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* desirable behavior.
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*/
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*/
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@ -822,7 +822,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
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ps.BindingTableEntryCount = 1;
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ps.BindingTableEntryCount = 1;
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}
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}
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/* SAMPLER_STATE prefetching is broken on Gfx11 - WA_1606682166 */
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/* SAMPLER_STATE prefetching is broken on Gfx11 - Wa_1606682166 */
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if (GFX_VER == 11)
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if (GFX_VER == 11)
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ps.SamplerCount = 0;
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ps.SamplerCount = 0;
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@ -1616,7 +1616,7 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
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vs.SingleVertexDispatch = false;
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vs.SingleVertexDispatch = false;
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#endif
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#endif
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vs.VectorMaskEnable = false;
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vs.VectorMaskEnable = false;
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/* WA_1606682166:
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/* Wa_1606682166:
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* Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
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* Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
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* Disable the Sampler state prefetch functionality in the SARB by
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* Disable the Sampler state prefetch functionality in the SARB by
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* programming 0xB000[30] to '1'.
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* programming 0xB000[30] to '1'.
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@ -1692,7 +1692,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
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hs.Enable = true;
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hs.Enable = true;
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hs.StatisticsEnable = true;
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hs.StatisticsEnable = true;
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hs.KernelStartPointer = tcs_bin->kernel.offset;
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hs.KernelStartPointer = tcs_bin->kernel.offset;
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/* WA_1606682166 */
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/* Wa_1606682166 */
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hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin);
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hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin);
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hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
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hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
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@ -1770,7 +1770,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
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ds.Enable = true;
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ds.Enable = true;
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ds.StatisticsEnable = true;
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ds.StatisticsEnable = true;
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ds.KernelStartPointer = tes_bin->kernel.offset;
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ds.KernelStartPointer = tes_bin->kernel.offset;
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/* WA_1606682166 */
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/* Wa_1606682166 */
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ds.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tes_bin);
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ds.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tes_bin);
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ds.BindingTableEntryCount = tes_bin->bind_map.surface_count;
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ds.BindingTableEntryCount = tes_bin->bind_map.surface_count;
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ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
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ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
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@ -1828,7 +1828,7 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline)
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gs.SingleProgramFlow = false;
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gs.SingleProgramFlow = false;
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gs.VectorMaskEnable = false;
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gs.VectorMaskEnable = false;
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/* WA_1606682166 */
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/* Wa_1606682166 */
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gs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(gs_bin);
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gs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(gs_bin);
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gs.BindingTableEntryCount = gs_bin->bind_map.surface_count;
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gs.BindingTableEntryCount = gs_bin->bind_map.surface_count;
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gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
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gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
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@ -2063,7 +2063,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
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ps.SingleProgramFlow = false;
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ps.SingleProgramFlow = false;
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ps.VectorMaskEnable = GFX_VER >= 8;
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ps.VectorMaskEnable = GFX_VER >= 8;
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/* WA_1606682166 */
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/* Wa_1606682166 */
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ps.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(fs_bin);
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ps.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(fs_bin);
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ps.BindingTableEntryCount = fs_bin->bind_map.surface_count;
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ps.BindingTableEntryCount = fs_bin->bind_map.surface_count;
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ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 ||
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ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 ||
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@ -2461,7 +2461,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
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cs_bin->kernel.offset +
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cs_bin->kernel.offset +
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brw_cs_prog_data_prog_offset(cs_prog_data, cs_params.simd_size),
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brw_cs_prog_data_prog_offset(cs_prog_data, cs_params.simd_size),
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/* WA_1606682166 */
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/* Wa_1606682166 */
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.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(cs_bin),
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.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(cs_bin),
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/* We add 1 because the CS indirect parameters buffer isn't accounted
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/* We add 1 because the CS indirect parameters buffer isn't accounted
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* for in bind_map.surface_count.
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* for in bind_map.surface_count.
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@ -365,7 +365,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
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l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM];
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l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM];
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#endif
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#endif
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#if GFX_VER == 11
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#if GFX_VER == 11
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/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be
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/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be
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* set in L3CNTLREG register. The default setting of the bit is not
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* set in L3CNTLREG register. The default setting of the bit is not
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* the desirable behavior.
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* the desirable behavior.
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*/
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*/
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@ -183,7 +183,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
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TEXEL_OFFSET_FIX_MASK |
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TEXEL_OFFSET_FIX_MASK |
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TEXEL_OFFSET_FIX_ENABLE);
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TEXEL_OFFSET_FIX_ENABLE);
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/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
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/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be set
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* in L3CNTLREG register. The default setting of the bit is not the
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* in L3CNTLREG register. The default setting of the bit is not the
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* desirable behavior.
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* desirable behavior.
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*/
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*/
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@ -2094,7 +2094,7 @@ static const struct brw_tracked_state genX(wm_state) = {
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#define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
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#define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
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pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
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pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
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/* WA_1606682166 */ \
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/* Wa_1606682166 */ \
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pkt.SamplerCount = \
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pkt.SamplerCount = \
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GFX_VER == 11 ? \
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GFX_VER == 11 ? \
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0 : \
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0 : \
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@ -3867,7 +3867,7 @@ genX(upload_ps)(struct brw_context *brw)
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*/
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*/
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ps.VectorMaskEnable = GFX_VER >= 8;
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ps.VectorMaskEnable = GFX_VER >= 8;
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/* WA_1606682166:
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/* Wa_1606682166:
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* "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
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* "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
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* Disable the Sampler state prefetch functionality in the SARB by
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* Disable the Sampler state prefetch functionality in the SARB by
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* programming 0xB000[30] to '1'."
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* programming 0xB000[30] to '1'."
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@ -4385,7 +4385,7 @@ genX(upload_cs_state)(struct brw_context *brw)
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const struct GENX(INTERFACE_DESCRIPTOR_DATA) idd = {
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const struct GENX(INTERFACE_DESCRIPTOR_DATA) idd = {
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.KernelStartPointer = ksp,
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.KernelStartPointer = ksp,
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.SamplerStatePointer = stage_state->sampler_offset,
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.SamplerStatePointer = stage_state->sampler_offset,
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/* WA_1606682166 */
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/* Wa_1606682166 */
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.SamplerCount = GFX_VER == 11 ? 0 :
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.SamplerCount = GFX_VER == 11 ? 0 :
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DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4),
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DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4),
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.BindingTablePointer = stage_state->bind_bo_offset,
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.BindingTablePointer = stage_state->bind_bo_offset,
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