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intel: Rename WA_### to Wa_### 

Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "WA_[[:digit:]]{10}" -rIl $SEARCH_PATH | xargs sed -ie "s/WA_\([[:digit:]]\{10\}\)/Wa_\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
This commit is contained in:
Anuj Phogat 2021-03-29 17:24:46 -07:00 committed by Marge Bot
parent f96c3b8b63
commit 051b7e1925
6 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gallium/drivers/iris/iris_state.c
View File

@ -758,7 +758,7 @@ iris_emit_l3_config(struct iris_batch *batch,
reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0;
#endif
#if GFX_VER == 11
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be set
* in L3CNTLREG register. The default setting of the bit is not the
* desirable behavior.
*/

2
src/intel/blorp/blorp_genX_exec.h
View File

@ -822,7 +822,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
ps.BindingTableEntryCount = 1;
}
/* SAMPLER_STATE prefetching is broken on Gfx11 - WA_1606682166 */
/* SAMPLER_STATE prefetching is broken on Gfx11 - Wa_1606682166 */
if (GFX_VER == 11)
ps.SamplerCount = 0;

12
src/intel/vulkan/genX_pipeline.c
View File

@ -1616,7 +1616,7 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
vs.SingleVertexDispatch = false;
#endif
vs.VectorMaskEnable = false;
/* WA_1606682166:
/* Wa_1606682166:
* Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
* Disable the Sampler state prefetch functionality in the SARB by
* programming 0xB000[30] to '1'.
@ -1692,7 +1692,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
hs.Enable = true;
hs.StatisticsEnable = true;
hs.KernelStartPointer = tcs_bin->kernel.offset;
/* WA_1606682166 */
/* Wa_1606682166 */
hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin);
hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
@ -1770,7 +1770,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
ds.Enable = true;
ds.StatisticsEnable = true;
ds.KernelStartPointer = tes_bin->kernel.offset;
/* WA_1606682166 */
/* Wa_1606682166 */
ds.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tes_bin);
ds.BindingTableEntryCount = tes_bin->bind_map.surface_count;
ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
@ -1828,7 +1828,7 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline)
gs.SingleProgramFlow = false;
gs.VectorMaskEnable = false;
/* WA_1606682166 */
/* Wa_1606682166 */
gs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(gs_bin);
gs.BindingTableEntryCount = gs_bin->bind_map.surface_count;
gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
@ -2063,7 +2063,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
ps.SingleProgramFlow = false;
ps.VectorMaskEnable = GFX_VER >= 8;
/* WA_1606682166 */
/* Wa_1606682166 */
ps.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(fs_bin);
ps.BindingTableEntryCount = fs_bin->bind_map.surface_count;
ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 ||
@ -2461,7 +2461,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
cs_bin->kernel.offset +
brw_cs_prog_data_prog_offset(cs_prog_data, cs_params.simd_size),
/* WA_1606682166 */
/* Wa_1606682166 */
.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(cs_bin),
/* We add 1 because the CS indirect parameters buffer isn't accounted
* for in bind_map.surface_count.

2
src/intel/vulkan/genX_state.c
View File

@ -365,7 +365,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM];
#endif
#if GFX_VER == 11
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be
/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be
* set in L3CNTLREG register. The default setting of the bit is not
* the desirable behavior.
*/

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View File

@ -183,7 +183,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
TEXEL_OFFSET_FIX_MASK |
TEXEL_OFFSET_FIX_ENABLE);
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
/* Wa_1406697149: Bit 9 "Error Detection Behavior Control" must be set
* in L3CNTLREG register. The default setting of the bit is not the
* desirable behavior.
*/

6
src/mesa/drivers/dri/i965/genX_state_upload.c
View File

@ -2094,7 +2094,7 @@ static const struct brw_tracked_state genX(wm_state) = {
#define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
/* WA_1606682166 */ \
/* Wa_1606682166 */ \
pkt.SamplerCount = \
GFX_VER == 11 ? \
0 : \
@ -3867,7 +3867,7 @@ genX(upload_ps)(struct brw_context *brw)
*/
ps.VectorMaskEnable = GFX_VER >= 8;
/* WA_1606682166:
/* Wa_1606682166:
* "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
* Disable the Sampler state prefetch functionality in the SARB by
* programming 0xB000[30] to '1'."
@ -4385,7 +4385,7 @@ genX(upload_cs_state)(struct brw_context *brw)
const struct GENX(INTERFACE_DESCRIPTOR_DATA) idd = {
.KernelStartPointer = ksp,
.SamplerStatePointer = stage_state->sampler_offset,
/* WA_1606682166 */
/* Wa_1606682166 */
.SamplerCount = GFX_VER == 11 ? 0 :
DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4),
.BindingTablePointer = stage_state->bind_bo_offset,