panfrost: Move depth/stencil/alpha to CSO create
Now that we can merge RSD state, there's no reason to pack this at draw-time. This is fun! Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10869>
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@ -517,12 +517,7 @@ panfrost_prepare_midgard_fs_state(struct panfrost_context *ctx,
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/* Reasons to disable early-Z from a shader perspective */
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bool late_z = fs->info.fs.can_discard || fs->info.writes_global ||
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fs->info.fs.writes_depth || fs->info.fs.writes_stencil ||
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(zsa->alpha_func != MALI_FUNC_ALWAYS);
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/* If either depth or stencil is enabled, discard matters */
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bool zs_enabled =
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(zsa->base.depth_enabled && zsa->base.depth_func != PIPE_FUNC_ALWAYS) ||
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zsa->base.stencil[0].enabled;
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((enum mali_func) zsa->base.alpha_func != MALI_FUNC_ALWAYS);
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bool has_blend_shader = false;
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@ -543,9 +538,9 @@ panfrost_prepare_midgard_fs_state(struct panfrost_context *ctx,
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* reads tilebuffer? flag to compensate */
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state->properties.midgard.shader_reads_tilebuffer =
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fs->info.fs.outputs_read ||
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(!zs_enabled && fs->info.fs.can_discard);
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(!zsa->enabled && fs->info.fs.can_discard);
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state->properties.midgard.shader_contains_discard =
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zs_enabled && fs->info.fs.can_discard;
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zsa->enabled && fs->info.fs.can_discard;
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}
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if (dev->quirks & MIDGARD_SFBD && ctx->pipe_framebuffer.nr_cbufs > 0) {
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@ -611,19 +606,11 @@ panfrost_prepare_fs_state(struct panfrost_context *ctx,
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state->multisample_misc.evaluate_per_sample =
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msaa && (ctx->min_samples > 1 || fs->info.fs.sample_shading);
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state->multisample_misc.depth_function = zsa->base.depth_enabled ?
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(enum mali_func) zsa->base.depth_func : MALI_FUNC_ALWAYS;
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state->multisample_misc.depth_write_mask = zsa->base.depth_writemask;
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state->multisample_misc.fixed_function_near_discard = rast->depth_clip_near;
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state->multisample_misc.fixed_function_far_discard = rast->depth_clip_far;
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state->multisample_misc.shader_depth_range_fixed = true;
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state->stencil_mask_misc.stencil_mask_front = zsa->stencil_mask_front;
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state->stencil_mask_misc.stencil_mask_back = zsa->stencil_mask_back;
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state->stencil_mask_misc.stencil_enable = zsa->base.stencil[0].enabled;
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state->stencil_mask_misc.alpha_to_coverage = alpha_to_coverage;
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state->stencil_mask_misc.alpha_test_compare_function = zsa->alpha_func;
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state->stencil_mask_misc.depth_range_1 = rast->offset_tri;
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state->stencil_mask_misc.depth_range_2 = rast->offset_tri;
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state->stencil_mask_misc.single_sampled_lines = !rast->multisample;
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@ -631,8 +618,6 @@ panfrost_prepare_fs_state(struct panfrost_context *ctx,
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state->depth_factor = rast->offset_scale;
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bool back_enab = zsa->base.stencil[1].enabled;
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state->stencil_front = zsa->stencil_front;
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state->stencil_back = zsa->stencil_back;
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state->stencil_front.reference_value = ctx->stencil_ref.ref_value[0];
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state->stencil_back.reference_value = ctx->stencil_ref.ref_value[back_enab ? 1 : 0];
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@ -648,6 +633,7 @@ panfrost_emit_frag_shader(struct panfrost_context *ctx,
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mali_ptr *blend_shaders)
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{
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struct panfrost_device *dev = pan_device(ctx->base.screen);
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const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
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struct panfrost_shader_state *fs =
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panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
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@ -673,6 +659,14 @@ panfrost_emit_frag_shader(struct panfrost_context *ctx,
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if (panfrost_fs_required(fs, ctx->blend, &ctx->pipe_framebuffer))
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pan_merge(rsd, fs->partial_rsd, RENDERER_STATE);
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/* Word 8, 9 Misc state */
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rsd.opaque[8] |= zsa->rsd_depth.opaque[0];
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rsd.opaque[9] |= zsa->rsd_stencil.opaque[0];
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/* Word 10, 11 Stencil Front and Back */
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rsd.opaque[10] |= zsa->stencil_front.opaque[0];
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rsd.opaque[11] |= zsa->stencil_back.opaque[0];
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memcpy(fragmeta, &rsd, sizeof(rsd));
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}
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@ -1392,36 +1392,62 @@ pan_pipe_to_stencil_op(enum pipe_stencil_op in)
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}
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static inline void
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pan_pipe_to_stencil(const struct pipe_stencil_state *in, struct MALI_STENCIL *out)
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pan_pipe_to_stencil(const struct pipe_stencil_state *in,
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struct mali_stencil_packed *out)
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{
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pan_prepare(out, STENCIL);
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out->mask = in->valuemask;
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out->compare_function = (enum mali_func) in->func;
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out->stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
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out->depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
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out->depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
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pan_pack(out, STENCIL, s) {
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s.mask = in->valuemask;
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s.compare_function = (enum mali_func) in->func;
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s.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
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s.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
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s.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
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}
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}
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static void *
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panfrost_create_depth_stencil_state(struct pipe_context *pipe,
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const struct pipe_depth_stencil_alpha_state *zsa)
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{
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struct panfrost_device *dev = pan_device(pipe->screen);
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struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
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so->base = *zsa;
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pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
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so->stencil_mask_front = zsa->stencil[0].writemask;
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/* Normalize (there's no separate enable) */
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if (!zsa->alpha_enabled)
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so->base.alpha_func = MALI_FUNC_ALWAYS;
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if (zsa->stencil[1].enabled) {
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pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
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so->stencil_mask_back = zsa->stencil[1].writemask;
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} else {
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so->stencil_back = so->stencil_front;
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so->stencil_mask_back = so->stencil_mask_front;
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/* Prepack relevant parts of the Renderer State Descriptor. They will
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* be ORed in at draw-time */
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pan_pack(&so->rsd_depth, MULTISAMPLE_MISC, cfg) {
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cfg.depth_function = zsa->depth_enabled ?
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(enum mali_func) zsa->depth_func : MALI_FUNC_ALWAYS;
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cfg.depth_write_mask = zsa->depth_writemask;
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}
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so->alpha_func = zsa->alpha_enabled ?
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(enum mali_func) zsa->alpha_func : MALI_FUNC_ALWAYS;
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pan_pack(&so->rsd_stencil, STENCIL_MASK_MISC, cfg) {
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cfg.stencil_enable = zsa->stencil[0].enabled;
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cfg.stencil_mask_front = zsa->stencil[0].writemask;
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cfg.stencil_mask_back = zsa->stencil[1].enabled ?
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zsa->stencil[1].writemask : zsa->stencil[0].writemask;
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if (dev->arch < 6) {
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cfg.alpha_test_compare_function =
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(enum mali_func) so->base.alpha_func;
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}
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}
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/* Stencil tests have their own words in the RSD */
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pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
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if (zsa->stencil[1].enabled)
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pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
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else
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so->stencil_back = so->stencil_front;
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so->enabled = zsa->stencil[0].enabled ||
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(zsa->depth_enabled && zsa->depth_func != PIPE_FUNC_ALWAYS);
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/* TODO: Bounds test should be easy */
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assert(!zsa->depth_bounds_test);
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@ -257,13 +257,14 @@ struct panfrost_vertex_state {
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struct panfrost_zsa_state {
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struct pipe_depth_stencil_alpha_state base;
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enum mali_func alpha_func;
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/* Precomputed stencil state */
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struct MALI_STENCIL stencil_front;
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struct MALI_STENCIL stencil_back;
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u8 stencil_mask_front;
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u8 stencil_mask_back;
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/* Is any depth, stencil, or alpha testing enabled? */
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bool enabled;
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/* Prepacked words from the RSD */
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struct mali_multisample_misc_packed rsd_depth;
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struct mali_stencil_mask_misc_packed rsd_stencil;
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struct mali_stencil_packed stencil_front, stencil_back;
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};
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struct panfrost_sampler_state {
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