amd: rename SIENNA -> SIENNA_CICHLID

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>
This commit is contained in:
Marek Olšák 2020-07-27 19:11:11 -04:00 committed by Marge Bot
parent ccfe9813fb
commit 037b84df11
9 changed files with 13 additions and 13 deletions

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@ -97,7 +97,7 @@
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
#define AMDGPU_NAVI14_RANGE 0x14, 0x28
#define AMDGPU_SIENNA_RANGE 0x28, 0x32
#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
@ -145,6 +145,6 @@
#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
#define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12)
#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
#define ASICREV_IS_SIENNA_M(r) ASICREV_IS(r, SIENNA)
#define ASICREV_IS_SIENNA_CICHLID(r) ASICREV_IS(r, SIENNA_CICHLID)
#endif // _AMDGPU_ASIC_ADDR_H

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@ -922,7 +922,7 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
case FAMILY_NV:
m_settings.isDcn2 = 1;
if (ASICREV_IS_SIENNA_M(chipRevision))
if (ASICREV_IS_SIENNA_CICHLID(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;

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@ -409,7 +409,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
identify_chip(NAVI10);
identify_chip(NAVI12);
identify_chip(NAVI14);
identify_chip(SIENNA);
identify_chip(SIENNA_CICHLID);
break;
}
@ -419,7 +419,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
return false;
}
if (info->family >= CHIP_SIENNA)
if (info->family >= CHIP_SIENNA_CICHLID)
info->chip_class = GFX10_3;
else if (info->family >= CHIP_NAVI10)
info->chip_class = GFX10;
@ -741,7 +741,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
case CHIP_RENOIR:
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_SIENNA:
case CHIP_SIENNA_CICHLID:
pc_lines = 1024;
break;
case CHIP_NAVI14:

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@ -102,7 +102,7 @@ enum radeon_family {
CHIP_NAVI10,
CHIP_NAVI12,
CHIP_NAVI14,
CHIP_SIENNA,
CHIP_SIENNA_CICHLID,
CHIP_LAST,
};

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@ -156,7 +156,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
return "gfx1011";
case CHIP_NAVI14:
return "gfx1012";
case CHIP_SIENNA:
case CHIP_SIENNA_CICHLID:
return "gfx1030";
default:
return "";

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@ -80,7 +80,7 @@ static void radv_null_winsys_query_info(struct radeon_winsys *rws,
info->family = i;
info->name = "OVERRIDDEN";
if (i >= CHIP_SIENNA)
if (i >= CHIP_SIENNA_CICHLID)
info->chip_class = GFX10_3;
else if (i >= CHIP_NAVI10)
info->chip_class = GFX10;

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@ -826,7 +826,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9)
? align(dec->base.width, 64)
: align(dec->base.width, 32);
if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA &&
if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA_CICHLID &&
dec->stream_type == RDECODE_CODEC_VP9)
decode->db_aligned_height = align(dec->base.height, 64);
@ -1589,7 +1589,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->jpg.direct_reg = true;
break;
case CHIP_ARCTURUS:
case CHIP_SIENNA:
case CHIP_SIENNA_CICHLID:
dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;

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@ -441,7 +441,7 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
goto error;
}
if (sscreen->info.family >= CHIP_SIENNA)
if (sscreen->info.family >= CHIP_SIENNA_CICHLID)
radeon_enc_3_0_init(enc);
else if (sscreen->info.family >= CHIP_RENOIR)
radeon_enc_2_0_init(enc);

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@ -63,7 +63,7 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws)
ws->info.family = i;
ws->info.name = "GCN-NOOP";
if (i >= CHIP_SIENNA)
if (i >= CHIP_SIENNA_CICHLID)
ws->info.chip_class = GFX10_3;
else if (i >= CHIP_NAVI10)
ws->info.chip_class = GFX10;