radv/query: handle multiview timestamp queries.
For each view bit we need to emit a timestamp query. Fixes: dEQP-VK.multiview.queries* Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
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@ -1233,42 +1233,49 @@ void radv_CmdWriteTimestamp(
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radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 5);
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28);
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int num_queries = 1;
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if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
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num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);
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switch(pipelineStage) {
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case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
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radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
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COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
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COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, query_va);
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radeon_emit(cs, query_va >> 32);
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_ME));
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radeon_emit(cs, avail_va);
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radeon_emit(cs, avail_va >> 32);
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radeon_emit(cs, 1);
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break;
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default:
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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mec,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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3, query_va, 0, 0);
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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mec,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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1, avail_va, 0, 1);
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break;
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for (unsigned i = 0; i < num_queries; i++) {
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switch(pipelineStage) {
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case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
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radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
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radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
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COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
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COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, query_va);
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radeon_emit(cs, query_va >> 32);
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radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
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radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
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S_370_WR_CONFIRM(1) |
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S_370_ENGINE_SEL(V_370_ME));
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radeon_emit(cs, avail_va);
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radeon_emit(cs, avail_va >> 32);
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radeon_emit(cs, 1);
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break;
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default:
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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mec,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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3, query_va, 0, 0);
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si_cs_emit_write_event_eop(cs,
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false,
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cmd_buffer->device->physical_device->rad_info.chip_class,
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mec,
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V_028A90_BOTTOM_OF_PIPE_TS, 0,
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1, avail_va, 0, 1);
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break;
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}
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query_va += pool->stride;
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avail_va += 4;
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}
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assert(cmd_buffer->cs->cdw <= cdw_max);
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}
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