i965: Use unsynchronized maps for the program cache on LLC platforms.
There's no reason to stall on pwrite - the CPU always appends to the buffer and never modifies existing contents, and the GPU never writes it. Further, the CPU always appends new data before submitting a batch that requires it. This code predates the unsynchronized mapping feature, so we simply didn't have the option when it was written. Ideally, we would do this for non-LLC platforms too, but unsynchronized mapping support only exists for LLC systems. Saves a bunch of stall avoidance copies when uploading shaders. v2: Rebase on changes to previous patch. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> [v1]
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@ -172,14 +172,23 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t new_size)
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drm_intel_bo *new_bo;
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new_bo = drm_intel_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
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if (brw->has_llc)
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drm_intel_gem_bo_map_unsynchronized(new_bo);
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/* Copy any existing data that needs to be saved. */
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if (cache->next_offset != 0) {
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drm_intel_bo_map(cache->bo, false);
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drm_intel_bo_subdata(new_bo, 0, cache->next_offset, cache->bo->virtual);
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drm_intel_bo_unmap(cache->bo);
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if (brw->has_llc) {
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memcpy(new_bo->virtual, cache->bo->virtual, cache->next_offset);
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} else {
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drm_intel_bo_map(cache->bo, false);
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drm_intel_bo_subdata(new_bo, 0, cache->next_offset,
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cache->bo->virtual);
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drm_intel_bo_unmap(cache->bo);
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}
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}
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if (brw->has_llc)
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drm_intel_bo_unmap(cache->bo);
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drm_intel_bo_unreference(cache->bo);
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cache->bo = new_bo;
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cache->bo_used_by_gpu = false;
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@ -200,6 +209,7 @@ brw_try_upload_using_copy(struct brw_cache *cache,
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const void *data,
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const void *aux)
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{
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struct brw_context *brw = cache->brw;
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int i;
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struct brw_cache_item *item;
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@ -221,9 +231,11 @@ brw_try_upload_using_copy(struct brw_cache *cache,
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continue;
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}
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drm_intel_bo_map(cache->bo, false);
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if (!brw->has_llc)
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drm_intel_bo_map(cache->bo, false);
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ret = memcmp(cache->bo->virtual + item->offset, data, item->size);
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drm_intel_bo_unmap(cache->bo);
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if (!brw->has_llc)
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drm_intel_bo_unmap(cache->bo);
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if (ret)
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continue;
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@ -256,7 +268,7 @@ brw_upload_item_data(struct brw_cache *cache,
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/* If we would block on writing to an in-use program BO, just
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* recreate it.
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*/
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if (cache->bo_used_by_gpu) {
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if (!brw->has_llc && cache->bo_used_by_gpu) {
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perf_debug("Copying busy program cache buffer.\n");
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brw_cache_new_bo(cache, cache->bo->size);
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}
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@ -279,6 +291,7 @@ brw_upload_cache(struct brw_cache *cache,
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uint32_t *out_offset,
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void *out_aux)
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{
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struct brw_context *brw = cache->brw;
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struct brw_cache_item *item = CALLOC_STRUCT(brw_cache_item);
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GLuint hash;
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void *tmp;
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@ -319,7 +332,11 @@ brw_upload_cache(struct brw_cache *cache,
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cache->n_items++;
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/* Copy data to the buffer */
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drm_intel_bo_subdata(cache->bo, item->offset, data_size, data);
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if (brw->has_llc) {
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memcpy((char *) cache->bo->virtual + item->offset, data, data_size);
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} else {
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drm_intel_bo_subdata(cache->bo, item->offset, data_size, data);
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}
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*out_offset = item->offset;
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*(void **)out_aux = (void *)((char *)item->key + item->key_size);
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@ -341,6 +358,8 @@ brw_init_caches(struct brw_context *brw)
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cache->bo = drm_intel_bo_alloc(brw->bufmgr,
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"program cache",
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4096, 64);
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if (brw->has_llc)
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drm_intel_gem_bo_map_unsynchronized(cache->bo);
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cache->aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
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cache->aux_compare[BRW_GS_PROG] = brw_gs_prog_data_compare;
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@ -407,6 +426,8 @@ brw_destroy_cache(struct brw_context *brw, struct brw_cache *cache)
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DBG("%s\n", __FUNCTION__);
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if (brw->has_llc)
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drm_intel_bo_unmap(cache->bo);
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drm_intel_bo_unreference(cache->bo);
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cache->bo = NULL;
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brw_clear_cache(brw, cache);
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