compiler: add shader_info.vs.blit_sgprs_amd
for internal radeonsi shaders
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e300365197
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028dbd35ba
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@ -158,6 +158,13 @@ typedef struct shader_info {
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/* Which inputs are doubles */
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/* Which inputs are doubles */
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uint64_t double_inputs;
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uint64_t double_inputs;
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/* For AMD-specific driver-internal shaders. It replaces vertex
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* buffer loads with code generating VS inputs from scalar registers.
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*
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* Valid values: SI_VS_BLIT_SGPRS_POS_*
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*/
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unsigned blit_sgprs_amd;
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/* True if the shader writes position in window space coordinates pre-transform */
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/* True if the shader writes position in window space coordinates pre-transform */
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bool window_space_position;
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bool window_space_position;
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} vs;
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} vs;
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@ -2106,6 +2106,9 @@ ttn_compile_init(const void *tgsi_tokens,
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case TGSI_PROPERTY_NEXT_SHADER:
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case TGSI_PROPERTY_NEXT_SHADER:
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s->info.next_stage = tgsi_processor_to_shader_stage(value);
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s->info.next_stage = tgsi_processor_to_shader_stage(value);
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break;
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break;
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case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
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s->info.vs.blit_sgprs_amd = value;
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break;
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default:
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default:
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if (value) {
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if (value) {
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fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
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fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
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@ -424,6 +424,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
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info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
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nir->info.vs.window_space_position;
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nir->info.vs.window_space_position;
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info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
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nir->info.vs.blit_sgprs_amd;
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}
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}
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if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
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if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
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