compiler: add shader_info.vs.blit_sgprs_amd

for internal radeonsi shaders

src/compiler/shader_info.h

@@ -158,6 +158,13 @@ typedef struct shader_info {
          /* Which inputs are doubles */
          uint64_t double_inputs;
 
+         /* For AMD-specific driver-internal shaders. It replaces vertex
+          * buffer loads with code generating VS inputs from scalar registers.
+          *
+          * Valid values: SI_VS_BLIT_SGPRS_POS_*
+          */
+         unsigned blit_sgprs_amd;
+
          /* True if the shader writes position in window space coordinates pre-transform */
          bool window_space_position;
       } vs;

src/gallium/auxiliary/nir/tgsi_to_nir.c

@@ -2106,6 +2106,9 @@ ttn_compile_init(const void *tgsi_tokens,
       case TGSI_PROPERTY_NEXT_SHADER:
          s->info.next_stage = tgsi_processor_to_shader_stage(value);
          break;
+      case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
+         s->info.vs.blit_sgprs_amd = value;
+         break;
       default:
          if (value) {
             fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",

src/gallium/drivers/radeonsi/si_shader_nir.c

@@ -424,6 +424,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
 	if (nir->info.stage == MESA_SHADER_VERTEX) {
 		info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
 			nir->info.vs.window_space_position;
+		info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
+			nir->info.vs.blit_sgprs_amd;
 	}
 
 	if (nir->info.stage == MESA_SHADER_TESS_CTRL) {