pan/mdg: Allow Z/S writes to use any 2nd stage unit
This ensures there will not be dependency problems if we emit a move that tries to read from a parallel instruction. No shader-db changes. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5513>
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@ -946,6 +946,73 @@ mir_schedule_ldst(
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return out;
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return out;
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}
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}
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static void
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mir_schedule_zs_write(
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compiler_context *ctx,
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struct midgard_predicate *predicate,
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midgard_instruction **instructions,
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BITSET_WORD *worklist, unsigned len,
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midgard_instruction *branch,
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midgard_instruction **smul,
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midgard_instruction **vadd,
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midgard_instruction **vlut,
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bool stencil)
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{
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bool success = false;
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unsigned idx = stencil ? 3 : 2;
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unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[idx];
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predicate->dest = src;
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predicate->mask = 0x1;
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midgard_instruction **units[] = { smul, vadd, vlut };
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unsigned unit_names[] = { UNIT_SMUL, UNIT_VADD, UNIT_VLUT };
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for (unsigned i = 0; i < 3; ++i) {
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if (*(units[i]))
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continue;
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predicate->unit = unit_names[i];
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midgard_instruction *ins =
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mir_choose_instruction(instructions, worklist, len, predicate);
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if (ins) {
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ins->unit = unit_names[i];
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*(units[i]) = ins;
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success |= true;
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break;
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}
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}
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predicate->dest = predicate->mask = 0;
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if (success)
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return;
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midgard_instruction *mov = ralloc(ctx, midgard_instruction);
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*mov = v_mov(src, make_compiler_temp(ctx));
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mov->mask = 0x1;
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branch->src[idx] = mov->dest;
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if (stencil) {
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unsigned swizzle = (branch->src[0] == ~0) ? COMPONENT_Y : COMPONENT_X;
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for (unsigned c = 0; c < 16; ++c)
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mov->swizzle[1][c] = swizzle;
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}
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for (unsigned i = 0; i < 3; ++i) {
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if (!(*(units[i]))) {
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*(units[i]) = mov;
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mov->unit = unit_names[i];
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return;
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}
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}
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unreachable("Could not schedule Z/S move to any unit");
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}
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static midgard_bundle
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static midgard_bundle
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mir_schedule_alu(
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mir_schedule_alu(
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compiler_context *ctx,
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compiler_context *ctx,
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@ -1037,64 +1104,11 @@ mir_schedule_alu(
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branch->dest_type = vadd->dest_type;
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branch->dest_type = vadd->dest_type;
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}
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}
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if (writeout & PAN_WRITEOUT_Z) {
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if (writeout & PAN_WRITEOUT_Z)
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/* Depth writeout */
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mir_schedule_zs_write(ctx, &predicate, instructions, worklist, len, branch, &smul, &vadd, &vlut, false);
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unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[2];
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if (writeout & PAN_WRITEOUT_S)
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mir_schedule_zs_write(ctx, &predicate, instructions, worklist, len, branch, &smul, &vadd, &vlut, true);
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predicate.unit = UNIT_SMUL;
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predicate.dest = src;
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predicate.mask = 0x1;
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midgard_instruction *z_store;
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z_store = mir_choose_instruction(instructions, worklist, len, &predicate);
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predicate.dest = predicate.mask = 0;
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if (!z_store) {
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z_store = ralloc(ctx, midgard_instruction);
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*z_store = v_mov(src, make_compiler_temp(ctx));
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branch->src[2] = z_store->dest;
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}
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smul = z_store;
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smul->unit = UNIT_SMUL;
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}
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if (writeout & PAN_WRITEOUT_S) {
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/* Stencil writeout */
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unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch->src[3];
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predicate.unit = UNIT_VLUT;
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predicate.dest = src;
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predicate.mask = 0x1;
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midgard_instruction *z_store;
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z_store = mir_choose_instruction(instructions, worklist, len, &predicate);
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predicate.dest = predicate.mask = 0;
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if (!z_store) {
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z_store = ralloc(ctx, midgard_instruction);
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*z_store = v_mov(src, make_compiler_temp(ctx));
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branch->src[3] = z_store->dest;
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z_store->mask = 0x1;
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unsigned swizzle = (branch->src[0] == ~0) ? COMPONENT_Y : COMPONENT_X;
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for (unsigned c = 0; c < 16; ++c)
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z_store->swizzle[1][c] = swizzle;
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}
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vlut = z_store;
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vlut->unit = UNIT_VLUT;
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}
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mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
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mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
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