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ilo: add genhw headers 

All except genhw.h are generated by https://github.com/olvaffe/envytools/.
intel_chipset.h is deprecated.
This commit is contained in:
Chia-I Wu 2014-04-13 00:33:00 +08:00
parent d75a8799fd
commit 01e3e82a56
22 changed files with 3503 additions and 130 deletions
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116
src/gallium/drivers/ilo/genhw/gen_blitter.xml.h Normal file
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#ifndef GEN_BLITTER_XML
#define GEN_BLITTER_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_BLITTER_TYPE__MASK 0xe0000000
#define GEN6_BLITTER_TYPE__SHIFT 29
#define GEN6_BLITTER_TYPE_BLITTER (0x2 << 29)
#define GEN6_BLITTER_OPCODE__MASK 0x1fc00000
#define GEN6_BLITTER_OPCODE__SHIFT 22
#define GEN6_BLITTER_OPCODE_COLOR_BLT (0x40 << 22)
#define GEN6_BLITTER_OPCODE_SRC_COPY_BLT (0x43 << 22)
#define GEN6_BLITTER_OPCODE_XY_COLOR_BLT (0x50 << 22)
#define GEN6_BLITTER_OPCODE_XY_SRC_COPY_BLT (0x53 << 22)
#define GEN6_BLITTER_BR00_WRITE_A (0x1 << 21)
#define GEN6_BLITTER_BR00_WRITE_RGB (0x1 << 20)
#define GEN6_BLITTER_BR00_SRC_TILED (0x1 << 15)
#define GEN6_BLITTER_BR00_DST_TILED (0x1 << 11)
#define GEN6_BLITTER_LENGTH__MASK 0x0000003f
#define GEN6_BLITTER_LENGTH__SHIFT 0
#define GEN6_BLITTER_BR13_CLIP_ENABLE (0x1 << 30)
#define GEN6_BLITTER_BR13_DIR_RTL (0x1 << 30)
#define GEN6_BLITTER_BR13_FORMAT__MASK 0x03000000
#define GEN6_BLITTER_BR13_FORMAT__SHIFT 24
#define GEN6_BLITTER_BR13_FORMAT_8 (0x0 << 24)
#define GEN6_BLITTER_BR13_FORMAT_565 (0x1 << 24)
#define GEN6_BLITTER_BR13_FORMAT_1555 (0x2 << 24)
#define GEN6_BLITTER_BR13_FORMAT_8888 (0x3 << 24)
#define GEN6_BLITTER_BR13_ROP__MASK 0x00ff0000
#define GEN6_BLITTER_BR13_ROP__SHIFT 16
#define GEN6_BLITTER_BR13_ROP_SRCCOPY (0xcc << 16)
#define GEN6_BLITTER_BR13_ROP_PATCOPY (0xf0 << 16)
#define GEN6_BLITTER_BR13_DST_PITCH__MASK 0x0000ffff
#define GEN6_BLITTER_BR13_DST_PITCH__SHIFT 0
#define GEN6_BLITTER_BR11_SRC_PITCH__MASK 0x0000ffff
#define GEN6_BLITTER_BR11_SRC_PITCH__SHIFT 0
#define GEN6_BLITTER_BR14_DST_HEIGHT__MASK 0xffff0000
#define GEN6_BLITTER_BR14_DST_HEIGHT__SHIFT 16
#define GEN6_BLITTER_BR14_DST_WIDTH__MASK 0x0000ffff
#define GEN6_BLITTER_BR14_DST_WIDTH__SHIFT 0
#define GEN6_BLITTER_BR22_DST_Y1__MASK 0xffff0000
#define GEN6_BLITTER_BR22_DST_Y1__SHIFT 16
#define GEN6_BLITTER_BR22_DST_X1__MASK 0x0000ffff
#define GEN6_BLITTER_BR22_DST_X1__SHIFT 0
#define GEN6_BLITTER_BR23_DST_Y2__MASK 0xffff0000
#define GEN6_BLITTER_BR23_DST_Y2__SHIFT 16
#define GEN6_BLITTER_BR23_DST_X2__MASK 0x0000ffff
#define GEN6_BLITTER_BR23_DST_X2__SHIFT 0
#define GEN6_BLITTER_BR26_SRC_Y1__MASK 0xffff0000
#define GEN6_BLITTER_BR26_SRC_Y1__SHIFT 16
#define GEN6_BLITTER_BR26_SRC_X1__MASK 0x0000ffff
#define GEN6_BLITTER_BR26_SRC_X1__SHIFT 0
#define GEN6_COLOR_BLT__SIZE 5
#define GEN6_SRC_COPY_BLT__SIZE 6
#define GEN6_XY_COLOR_BLT__SIZE 6
#define GEN6_XY_SRC_COPY_BLT__SIZE 8
#endif /* GEN_BLITTER_XML */

461
src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h Normal file
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#ifndef GEN_EU_ISA_XML
#define GEN_EU_ISA_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_OPCODE_ILLEGAL 0x0
#define GEN6_OPCODE_MOV 0x1
#define GEN6_OPCODE_SEL 0x2
#define GEN6_OPCODE_MOVI 0x3
#define GEN6_OPCODE_NOT 0x4
#define GEN6_OPCODE_AND 0x5
#define GEN6_OPCODE_OR 0x6
#define GEN6_OPCODE_XOR 0x7
#define GEN6_OPCODE_SHR 0x8
#define GEN6_OPCODE_SHL 0x9
#define GEN6_OPCODE_DIM 0xa
#define GEN6_OPCODE_ASR 0xc
#define GEN6_OPCODE_CMP 0x10
#define GEN6_OPCODE_CMPN 0x11
#define GEN7_OPCODE_CSEL 0x12
#define GEN7_OPCODE_F32TO16 0x13
#define GEN7_OPCODE_F16TO32 0x14
#define GEN7_OPCODE_BFREV 0x17
#define GEN7_OPCODE_BFE 0x18
#define GEN7_OPCODE_BFI1 0x19
#define GEN7_OPCODE_BFI2 0x1a
#define GEN6_OPCODE_JMPI 0x20
#define GEN7_OPCODE_BRD 0x21
#define GEN6_OPCODE_IF 0x22
#define GEN7_OPCODE_BRC 0x23
#define GEN6_OPCODE_ELSE 0x24
#define GEN6_OPCODE_ENDIF 0x25
#define GEN6_OPCODE_CASE 0x26
#define GEN6_OPCODE_WHILE 0x27
#define GEN6_OPCODE_BREAK 0x28
#define GEN6_OPCODE_CONT 0x29
#define GEN6_OPCODE_HALT 0x2a
#define GEN75_OPCODE_CALLA 0x2b
#define GEN6_OPCODE_CALL 0x2c
#define GEN6_OPCODE_RETURN 0x2d
#define GEN6_OPCODE_WAIT 0x30
#define GEN6_OPCODE_SEND 0x31
#define GEN6_OPCODE_SENDC 0x32
#define GEN6_OPCODE_MATH 0x38
#define GEN6_OPCODE_ADD 0x40
#define GEN6_OPCODE_MUL 0x41
#define GEN6_OPCODE_AVG 0x42
#define GEN6_OPCODE_FRC 0x43
#define GEN6_OPCODE_RNDU 0x44
#define GEN6_OPCODE_RNDD 0x45
#define GEN6_OPCODE_RNDE 0x46
#define GEN6_OPCODE_RNDZ 0x47
#define GEN6_OPCODE_MAC 0x48
#define GEN6_OPCODE_MACH 0x49
#define GEN6_OPCODE_LZD 0x4a
#define GEN7_OPCODE_FBH 0x4b
#define GEN7_OPCODE_FBL 0x4c
#define GEN7_OPCODE_CBIT 0x4d
#define GEN7_OPCODE_ADDC 0x4e
#define GEN7_OPCODE_SUBB 0x4f
#define GEN6_OPCODE_SAD2 0x50
#define GEN6_OPCODE_SADA2 0x51
#define GEN6_OPCODE_DP4 0x54
#define GEN6_OPCODE_DPH 0x55
#define GEN6_OPCODE_DP3 0x56
#define GEN6_OPCODE_DP2 0x57
#define GEN6_OPCODE_LINE 0x59
#define GEN6_OPCODE_PLN 0x5a
#define GEN6_OPCODE_MAD 0x5b
#define GEN6_OPCODE_LRP 0x5c
#define GEN6_OPCODE_NOP 0x7e
#define GEN6_ALIGN_1 0x0
#define GEN6_ALIGN_16 0x1
#define GEN6_MASKCTRL_NORMAL 0x0
#define GEN6_MASKCTRL_NOMASK 0x1
#define GEN6_DEPCTRL_NORMAL 0x0
#define GEN6_DEPCTRL_NODDCLR 0x1
#define GEN6_DEPCTRL_NODDCHK 0x2
#define GEN6_DEPCTRL_NEITHER 0x3
#define GEN6_QTRCTRL_1Q 0x0
#define GEN6_QTRCTRL_2Q 0x1
#define GEN6_QTRCTRL_3Q 0x2
#define GEN6_QTRCTRL_4Q 0x3
#define GEN6_QTRCTRL_1H 0x0
#define GEN6_QTRCTRL_2H 0x2
#define GEN6_THREADCTRL_NORMAL 0x0
#define GEN6_THREADCTRL_ATOMIC 0x1
#define GEN6_THREADCTRL_SWITCH 0x2
#define GEN6_PREDCTRL_NONE 0x0
#define GEN6_PREDCTRL_NORMAL 0x1
#define GEN6_PREDCTRL_ANYV 0x2
#define GEN6_PREDCTRL_ALLV 0x3
#define GEN6_PREDCTRL_ANY2H 0x4
#define GEN6_PREDCTRL_ALL2H 0x5
#define GEN6_PREDCTRL_X 0x2
#define GEN6_PREDCTRL_Y 0x3
#define GEN6_PREDCTRL_Z 0x4
#define GEN6_PREDCTRL_W 0x5
#define GEN6_PREDCTRL_ANY4H 0x6
#define GEN6_PREDCTRL_ALL4H 0x7
#define GEN6_PREDCTRL_ANY8H 0x8
#define GEN6_PREDCTRL_ALL8H 0x9
#define GEN6_PREDCTRL_ANY16H 0xa
#define GEN6_PREDCTRL_ALL16H 0xb
#define GEN7_PREDCTRL_ANY32H 0xc
#define GEN7_PREDCTRL_ALL32H 0xd
#define GEN6_EXECSIZE_1 0x0
#define GEN6_EXECSIZE_2 0x1
#define GEN6_EXECSIZE_4 0x2
#define GEN6_EXECSIZE_8 0x3
#define GEN6_EXECSIZE_16 0x4
#define GEN6_EXECSIZE_32 0x5
#define GEN6_COND_NORMAL 0x0
#define GEN6_COND_Z 0x1
#define GEN6_COND_NZ 0x2
#define GEN6_COND_G 0x3
#define GEN6_COND_GE 0x4
#define GEN6_COND_L 0x5
#define GEN6_COND_LE 0x6
#define GEN6_COND_O 0x8
#define GEN6_COND_U 0x9
#define GEN6_MATH_INV 0x1
#define GEN6_MATH_LOG 0x2
#define GEN6_MATH_EXP 0x3
#define GEN6_MATH_SQRT 0x4
#define GEN6_MATH_RSQ 0x5
#define GEN6_MATH_SIN 0x6
#define GEN6_MATH_COS 0x7
#define GEN6_MATH_FDIV 0x9
#define GEN6_MATH_POW 0xa
#define GEN6_MATH_INT_DIV 0xb
#define GEN6_MATH_INT_DIV_QUOTIENT 0xc
#define GEN6_MATH_INT_DIV_REMAINDER 0xd
#define GEN6_SFID_NULL 0x0
#define GEN6_SFID_SAMPLER 0x2
#define GEN6_SFID_GATEWAY 0x3
#define GEN6_SFID_DP_SAMPLER 0x4
#define GEN6_SFID_DP_RC 0x5
#define GEN6_SFID_URB 0x6
#define GEN6_SFID_SPAWNER 0x7
#define GEN6_SFID_VME 0x8
#define GEN6_SFID_DP_CC 0x9
#define GEN7_SFID_DP_DC0 0xa
#define GEN7_SFID_PI 0xb
#define GEN75_SFID_DP_DC1 0xc
#define GEN6_FILE_ARF 0x0
#define GEN6_FILE_GRF 0x1
#define GEN6_FILE_MRF 0x2
#define GEN6_FILE_IMM 0x3
#define GEN6_TYPE_UD 0x0
#define GEN6_TYPE_D 0x1
#define GEN6_TYPE_UW 0x2
#define GEN6_TYPE_W 0x3
#define GEN6_TYPE_UB 0x4
#define GEN6_TYPE_B 0x5
#define GEN7_TYPE_DF 0x6
#define GEN6_TYPE_F 0x7
#define GEN6_TYPE_UV_IMM 0x4
#define GEN6_TYPE_VF_IMM 0x5
#define GEN6_TYPE_V_IMM 0x6
#define GEN7_TYPE_F_3SRC 0x0
#define GEN7_TYPE_D_3SRC 0x1
#define GEN7_TYPE_UD_3SRC 0x2
#define GEN7_TYPE_DF_3SRC 0x3
#define GEN6_VERTSTRIDE_0 0x0
#define GEN6_VERTSTRIDE_1 0x1
#define GEN6_VERTSTRIDE_2 0x2
#define GEN6_VERTSTRIDE_4 0x3
#define GEN6_VERTSTRIDE_8 0x4
#define GEN6_VERTSTRIDE_16 0x5
#define GEN6_VERTSTRIDE_32 0x6
#define GEN6_VERTSTRIDE_VXH 0xf
#define GEN6_WIDTH_1 0x0
#define GEN6_WIDTH_2 0x1
#define GEN6_WIDTH_4 0x2
#define GEN6_WIDTH_8 0x3
#define GEN6_WIDTH_16 0x4
#define GEN6_HORZSTRIDE_0 0x0
#define GEN6_HORZSTRIDE_1 0x1
#define GEN6_HORZSTRIDE_2 0x2
#define GEN6_HORZSTRIDE_4 0x3
#define GEN6_ADDRMODE_DIRECT 0x0
#define GEN6_ADDRMODE_INDIRECT 0x1
#define GEN6_SWIZZLE_X 0x0
#define GEN6_SWIZZLE_Y 0x1
#define GEN6_SWIZZLE_Z 0x2
#define GEN6_SWIZZLE_W 0x3
#define GEN6_ARF_NULL 0x0
#define GEN6_ARF_A0 0x10
#define GEN6_ARF_ACC0 0x20
#define GEN6_ARF_F0 0x30
#define GEN6_ARF_SR0 0x70
#define GEN6_ARF_CR0 0x80
#define GEN6_ARF_N0 0x90
#define GEN6_ARF_IP 0xa0
#define GEN6_ARF_TDR 0xb0
#define GEN7_ARF_TM0 0xc0
#define GEN6_INST_DW0_SATURATE (0x1 << 31)
#define GEN6_INST_DW0_ACCWRCTRL (0x1 << 28)
#define GEN6_INST_DW0_CONDMODIFIER__MASK 0x0f000000
#define GEN6_INST_DW0_CONDMODIFIER__SHIFT 24
#define GEN6_INST_DW0_SFID__MASK 0x0f000000
#define GEN6_INST_DW0_SFID__SHIFT 24
#define GEN6_INST_DW0_FC__MASK 0x0f000000
#define GEN6_INST_DW0_FC__SHIFT 24
#define GEN6_INST_DW0_EXECSIZE__MASK 0x00e00000
#define GEN6_INST_DW0_EXECSIZE__SHIFT 21
#define GEN6_INST_DW0_PREDINV (0x1 << 20)
#define GEN6_INST_DW0_PREDCTRL__MASK 0x000f0000
#define GEN6_INST_DW0_PREDCTRL__SHIFT 16
#define GEN6_INST_DW0_THREADCTRL__MASK 0x0000c000
#define GEN6_INST_DW0_THREADCTRL__SHIFT 14
#define GEN6_INST_DW0_QTRCTRL__MASK 0x00003000
#define GEN6_INST_DW0_QTRCTRL__SHIFT 12
#define GEN6_INST_DW0_DEPCTRL__MASK 0x00000c00
#define GEN6_INST_DW0_DEPCTRL__SHIFT 10
#define GEN6_INST_DW0_MASKCTRL__MASK 0x00000200
#define GEN6_INST_DW0_MASKCTRL__SHIFT 9
#define GEN6_INST_DW0_ACCESSMODE__MASK 0x00000100
#define GEN6_INST_DW0_ACCESSMODE__SHIFT 8
#define GEN6_INST_DW0_OPCODE__MASK 0x0000007f
#define GEN6_INST_DW0_OPCODE__SHIFT 0
#define GEN6_INST_DW1_ADDRMODE__MASK 0x80000000
#define GEN6_INST_DW1_ADDRMODE__SHIFT 31
#define GEN6_INST_DW1_HORZSTRIDE__MASK 0x60000000
#define GEN6_INST_DW1_HORZSTRIDE__SHIFT 29
#define GEN6_INST_DW1_REG__MASK 0x1fe00000
#define GEN6_INST_DW1_REG__SHIFT 21
#define GEN6_INST_DW1_SUBREG__MASK 0x001f0000
#define GEN6_INST_DW1_SUBREG__SHIFT 16
#define GEN6_INST_DW1_ADDR_SUBREG__MASK 0x1c000000
#define GEN6_INST_DW1_ADDR_SUBREG__SHIFT 26
#define GEN6_INST_DW1_ADDR_IMM__MASK 0x03ff0000
#define GEN6_INST_DW1_ADDR_IMM__SHIFT 16
#define GEN6_INST_DW1_SUBREG_ALIGN16__MASK 0x00100000
#define GEN6_INST_DW1_SUBREG_ALIGN16__SHIFT 20
#define GEN6_INST_DW1_SUBREG_ALIGN16__SHR 4
#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__MASK 0x03f00000
#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__SHIFT 20
#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__SHR 4
#define GEN6_INST_DW1_WRITEMASK__MASK 0x000f0000
#define GEN6_INST_DW1_WRITEMASK__SHIFT 16
#define GEN7_INST_DW1_NIBCTRL (0x1 << 15)
#define GEN6_INST_DW1_SRC1_TYPE__MASK 0x00007000
#define GEN6_INST_DW1_SRC1_TYPE__SHIFT 12
#define GEN6_INST_DW1_SRC1_FILE__MASK 0x00000c00
#define GEN6_INST_DW1_SRC1_FILE__SHIFT 10
#define GEN6_INST_DW1_SRC0_TYPE__MASK 0x00000380
#define GEN6_INST_DW1_SRC0_TYPE__SHIFT 7
#define GEN6_INST_DW1_SRC0_FILE__MASK 0x00000060
#define GEN6_INST_DW1_SRC0_FILE__SHIFT 5
#define GEN6_INST_DW1_TYPE__MASK 0x0000001c
#define GEN6_INST_DW1_TYPE__SHIFT 2
#define GEN6_INST_DW1_FILE__MASK 0x00000003
#define GEN6_INST_DW1_FILE__SHIFT 0
#define GEN7_INST_DW2_FLAG_REG__MASK 0x04000000
#define GEN7_INST_DW2_FLAG_REG__SHIFT 26
#define GEN6_INST_DW2_FLAG_SUBREG__MASK 0x02000000
#define GEN6_INST_DW2_FLAG_SUBREG__SHIFT 25
#define GEN6_INST_DW2_VERTSTRIDE__MASK 0x01e00000
#define GEN6_INST_DW2_VERTSTRIDE__SHIFT 21
#define GEN6_INST_DW2_WIDTH__MASK 0x001c0000
#define GEN6_INST_DW2_WIDTH__SHIFT 18
#define GEN6_INST_DW2_HORZSTRIDE__MASK 0x00030000
#define GEN6_INST_DW2_HORZSTRIDE__SHIFT 16
#define GEN6_INST_DW2_SWIZZLE_W__MASK 0x000c0000
#define GEN6_INST_DW2_SWIZZLE_W__SHIFT 18
#define GEN6_INST_DW2_SWIZZLE_Z__MASK 0x00030000
#define GEN6_INST_DW2_SWIZZLE_Z__SHIFT 16
#define GEN6_INST_DW2_ADDRMODE__MASK 0x00008000
#define GEN6_INST_DW2_ADDRMODE__SHIFT 15
#define GEN6_INST_DW2_NEGATE (0x1 << 14)
#define GEN6_INST_DW2_ABSOLUTE (0x1 << 13)
#define GEN6_INST_DW2_REG__MASK 0x00001fe0
#define GEN6_INST_DW2_REG__SHIFT 5
#define GEN6_INST_DW2_SUBREG__MASK 0x0000001f
#define GEN6_INST_DW2_SUBREG__SHIFT 0
#define GEN6_INST_DW2_ADDR_SUBREG__MASK 0x00001c00
#define GEN6_INST_DW2_ADDR_SUBREG__SHIFT 10
#define GEN6_INST_DW2_ADDR_IMM__MASK 0x000003ff
#define GEN6_INST_DW2_ADDR_IMM__SHIFT 0
#define GEN6_INST_DW2_SUBREG_ALIGN16 (0x1 << 4)
#define GEN6_INST_DW2_SUBREG_ALIGN16__SHR 4
#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__MASK 0x000003f0
#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__SHIFT 4
#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__SHR 4
#define GEN6_INST_DW2_SWIZZLE_Y__MASK 0x0000000c
#define GEN6_INST_DW2_SWIZZLE_Y__SHIFT 2
#define GEN6_INST_DW2_SWIZZLE_X__MASK 0x00000003
#define GEN6_INST_DW2_SWIZZLE_X__SHIFT 0
#define GEN7_INST_DW3_FLAG_REG__MASK 0x04000000
#define GEN7_INST_DW3_FLAG_REG__SHIFT 26
#define GEN6_INST_DW3_FLAG_SUBREG__MASK 0x02000000
#define GEN6_INST_DW3_FLAG_SUBREG__SHIFT 25
#define GEN6_INST_DW3_VERTSTRIDE__MASK 0x01e00000
#define GEN6_INST_DW3_VERTSTRIDE__SHIFT 21
#define GEN6_INST_DW3_WIDTH__MASK 0x001c0000
#define GEN6_INST_DW3_WIDTH__SHIFT 18
#define GEN6_INST_DW3_HORZSTRIDE__MASK 0x00030000
#define GEN6_INST_DW3_HORZSTRIDE__SHIFT 16
#define GEN6_INST_DW3_SWIZZLE_W__MASK 0x000c0000
#define GEN6_INST_DW3_SWIZZLE_W__SHIFT 18
#define GEN6_INST_DW3_SWIZZLE_Z__MASK 0x00030000
#define GEN6_INST_DW3_SWIZZLE_Z__SHIFT 16
#define GEN6_INST_DW3_ADDRMODE__MASK 0x00008000
#define GEN6_INST_DW3_ADDRMODE__SHIFT 15
#define GEN6_INST_DW3_NEGATE (0x1 << 14)
#define GEN6_INST_DW3_ABSOLUTE (0x1 << 13)
#define GEN6_INST_DW3_REG__MASK 0x00001fe0
#define GEN6_INST_DW3_REG__SHIFT 5
#define GEN6_INST_DW3_SUBREG__MASK 0x0000001f
#define GEN6_INST_DW3_SUBREG__SHIFT 0
#define GEN6_INST_DW3_ADDR_SUBREG__MASK 0x00001c00
#define GEN6_INST_DW3_ADDR_SUBREG__SHIFT 10
#define GEN6_INST_DW3_ADDR_IMM__MASK 0x000003ff
#define GEN6_INST_DW3_ADDR_IMM__SHIFT 0
#define GEN6_INST_DW3_SUBREG_ALIGN16 (0x1 << 4)
#define GEN6_INST_DW3_SUBREG_ALIGN16__SHR 4
#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__MASK 0x000003f0
#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__SHIFT 4
#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__SHR 4
#define GEN6_INST_DW3_SWIZZLE_Y__MASK 0x0000000c
#define GEN6_INST_DW3_SWIZZLE_Y__SHIFT 2
#define GEN6_INST_DW3_SWIZZLE_X__MASK 0x00000003
#define GEN6_INST_DW3_SWIZZLE_X__SHIFT 0
#define GEN6_3SRC_DW0_SATURATE (0x1 << 31)
#define GEN6_3SRC_DW0_ACCWRCTRL (0x1 << 28)
#define GEN6_3SRC_DW0_CONDMODIFIER__MASK 0x0f000000
#define GEN6_3SRC_DW0_CONDMODIFIER__SHIFT 24
#define GEN6_3SRC_DW0_SFID__MASK 0x0f000000
#define GEN6_3SRC_DW0_SFID__SHIFT 24
#define GEN6_3SRC_DW0_FC__MASK 0x0f000000
#define GEN6_3SRC_DW0_FC__SHIFT 24
#define GEN6_3SRC_DW0_EXECSIZE__MASK 0x00e00000
#define GEN6_3SRC_DW0_EXECSIZE__SHIFT 21
#define GEN6_3SRC_DW0_PREDINV (0x1 << 20)
#define GEN6_3SRC_DW0_PREDCTRL__MASK 0x000f0000
#define GEN6_3SRC_DW0_PREDCTRL__SHIFT 16
#define GEN6_3SRC_DW0_THREADCTRL__MASK 0x0000c000
#define GEN6_3SRC_DW0_THREADCTRL__SHIFT 14
#define GEN6_3SRC_DW0_QTRCTRL__MASK 0x00003000
#define GEN6_3SRC_DW0_QTRCTRL__SHIFT 12
#define GEN6_3SRC_DW0_DEPCTRL__MASK 0x00000c00
#define GEN6_3SRC_DW0_DEPCTRL__SHIFT 10
#define GEN6_3SRC_DW0_MASKCTRL__MASK 0x00000200
#define GEN6_3SRC_DW0_MASKCTRL__SHIFT 9
#define GEN6_3SRC_DW0_ACCESSMODE__MASK 0x00000100
#define GEN6_3SRC_DW0_ACCESSMODE__SHIFT 8
#define GEN6_3SRC_DW0_OPCODE__MASK 0x0000007f
#define GEN6_3SRC_DW0_OPCODE__SHIFT 0
#define GEN6_3SRC_DW1_REG__MASK 0xff000000
#define GEN6_3SRC_DW1_REG__SHIFT 24
#define GEN6_3SRC_DW1_SUBREG__MASK 0x00e00000
#define GEN6_3SRC_DW1_SUBREG__SHIFT 21
#define GEN6_3SRC_DW1_SUBREG__SHR 2
#define GEN6_3SRC_DW1_WRITEMASK__MASK 0x001e0000
#define GEN6_3SRC_DW1_WRITEMASK__SHIFT 17
#define GEN7_3SRC_DW1_NIBCTRL (0x1 << 15)
#define GEN7_3SRC_DW1_TYPE__MASK 0x00003000
#define GEN7_3SRC_DW1_TYPE__SHIFT 12
#define GEN7_3SRC_DW1_SRC_TYPE__MASK 0x00000c00
#define GEN7_3SRC_DW1_SRC_TYPE__SHIFT 10
#define GEN6_3SRC_DW1_SRC2_NEGATE (0x1 << 9)
#define GEN6_3SRC_DW1_SRC2_ABSOLUTE (0x1 << 8)
#define GEN6_3SRC_DW1_SRC1_NEGATE (0x1 << 7)
#define GEN6_3SRC_DW1_SRC1_ABSOLUTE (0x1 << 6)
#define GEN6_3SRC_DW1_SRC0_NEGATE (0x1 << 5)
#define GEN6_3SRC_DW1_SRC0_ABSOLUTE (0x1 << 4)
#define GEN7_3SRC_DW1_FLAG_REG__MASK 0x00000004
#define GEN7_3SRC_DW1_FLAG_REG__SHIFT 2
#define GEN6_3SRC_DW1_FLAG_SUBREG__MASK 0x00000002
#define GEN6_3SRC_DW1_FLAG_SUBREG__SHIFT 1
#define GEN6_3SRC_DW1_FILE_MRF (0x1 << 0)
#define GEN6_3SRC_SRC_2__MASK 0x7ffffc0000000000ULL
#define GEN6_3SRC_SRC_2__SHIFT 42
#define GEN6_3SRC_SRC_2_REG__MASK 0x3fc0000000000000ULL
#define GEN6_3SRC_SRC_2_REG__SHIFT 54
#define GEN6_3SRC_SRC_2_SUBREG__MASK 0x0038000000000000ULL
#define GEN6_3SRC_SRC_2_SUBREG__SHIFT 51
#define GEN6_3SRC_SRC_2_SUBREG__SHR 2
#define GEN6_3SRC_SRC_2_SWIZZLE_W__MASK 0x0006000000000000ULL
#define GEN6_3SRC_SRC_2_SWIZZLE_W__SHIFT 49
#define GEN6_3SRC_SRC_2_SWIZZLE_Z__MASK 0x0001800000000000ULL
#define GEN6_3SRC_SRC_2_SWIZZLE_Z__SHIFT 47
#define GEN6_3SRC_SRC_2_SWIZZLE_Y__MASK 0x0000600000000000ULL
#define GEN6_3SRC_SRC_2_SWIZZLE_Y__SHIFT 45
#define GEN6_3SRC_SRC_2_SWIZZLE_X__MASK 0x0000180000000000ULL
#define GEN6_3SRC_SRC_2_SWIZZLE_X__SHIFT 43
#define GEN6_3SRC_SRC_2_REPCTRL (0x1 << 42)
#define GEN6_3SRC_SRC_1__MASK 0x000003ffffe00000ULL
#define GEN6_3SRC_SRC_1__SHIFT 21
#define GEN6_3SRC_SRC_1_REG__MASK 0x000001fe00000000ULL
#define GEN6_3SRC_SRC_1_REG__SHIFT 33
#define GEN6_3SRC_SRC_1_SUBREG__MASK 0x00000001c0000000ULL
#define GEN6_3SRC_SRC_1_SUBREG__SHIFT 30
#define GEN6_3SRC_SRC_1_SUBREG__SHR 2
#define GEN6_3SRC_SRC_1_SWIZZLE_W__MASK 0x30000000
#define GEN6_3SRC_SRC_1_SWIZZLE_W__SHIFT 28
#define GEN6_3SRC_SRC_1_SWIZZLE_Z__MASK 0x0c000000
#define GEN6_3SRC_SRC_1_SWIZZLE_Z__SHIFT 26
#define GEN6_3SRC_SRC_1_SWIZZLE_Y__MASK 0x03000000
#define GEN6_3SRC_SRC_1_SWIZZLE_Y__SHIFT 24
#define GEN6_3SRC_SRC_1_SWIZZLE_X__MASK 0x00c00000
#define GEN6_3SRC_SRC_1_SWIZZLE_X__SHIFT 22
#define GEN6_3SRC_SRC_1_REPCTRL (0x1 << 21)
#define GEN6_3SRC_SRC_0__MASK 0x001fffff
#define GEN6_3SRC_SRC_0__SHIFT 0
#define GEN6_3SRC_SRC_0_REG__MASK 0x000ff000
#define GEN6_3SRC_SRC_0_REG__SHIFT 12
#define GEN6_3SRC_SRC_0_SUBREG__MASK 0x00000e00
#define GEN6_3SRC_SRC_0_SUBREG__SHIFT 9
#define GEN6_3SRC_SRC_0_SUBREG__SHR 2
#define GEN6_3SRC_SRC_0_SWIZZLE_W__MASK 0x00000180
#define GEN6_3SRC_SRC_0_SWIZZLE_W__SHIFT 7
#define GEN6_3SRC_SRC_0_SWIZZLE_Z__MASK 0x00000060
#define GEN6_3SRC_SRC_0_SWIZZLE_Z__SHIFT 5
#define GEN6_3SRC_SRC_0_SWIZZLE_Y__MASK 0x00000018
#define GEN6_3SRC_SRC_0_SWIZZLE_Y__SHIFT 3
#define GEN6_3SRC_SRC_0_SWIZZLE_X__MASK 0x00000006
#define GEN6_3SRC_SRC_0_SWIZZLE_X__SHIFT 1
#define GEN6_3SRC_SRC_0_REPCTRL (0x1 << 0)
#endif /* GEN_EU_ISA_XML */

219
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#ifndef GEN_EU_MESSAGE_XML
#define GEN_EU_MESSAGE_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_MSG_URB_WRITE 0x0
#define GEN6_MSG_URB_FF_SYNC 0x1
#define GEN7_MSG_URB_WRITE_HWORD 0x0
#define GEN7_MSG_URB_WRITE_OWORD 0x1
#define GEN7_MSG_URB_READ_HWORD 0x2
#define GEN7_MSG_URB_READ_OWORD 0x3
#define GEN7_MSG_URB_ATOMIC_MOV 0x4
#define GEN7_MSG_URB_ATOMIC_INC 0x5
#define GEN6_MSG_SAMPLER_SIMD4X2 0x0
#define GEN6_MSG_SAMPLER_SIMD8 0x1
#define GEN6_MSG_SAMPLER_SIMD16 0x2
#define GEN6_MSG_SAMPLER_SIMD32_64 0x3
#define GEN6_MSG_SAMPLER_SAMPLE 0x0
#define GEN6_MSG_SAMPLER_SAMPLE_B 0x1
#define GEN6_MSG_SAMPLER_SAMPLE_L 0x2
#define GEN6_MSG_SAMPLER_SAMPLE_C 0x3
#define GEN6_MSG_SAMPLER_SAMPLE_D 0x4
#define GEN6_MSG_SAMPLER_SAMPLE_B_C 0x5
#define GEN6_MSG_SAMPLER_SAMPLE_L_C 0x6
#define GEN6_MSG_SAMPLER_LD 0x7
#define GEN6_MSG_SAMPLER_GATHER4 0x8
#define GEN6_MSG_SAMPLER_LOD 0x9
#define GEN6_MSG_SAMPLER_RESINFO 0xa
#define GEN6_MSG_SAMPLER_SAMPLEINFO 0xb
#define GEN7_MSG_SAMPLER_GATHER4_C 0x10
#define GEN7_MSG_SAMPLER_GATHER4_PO 0x11
#define GEN7_MSG_SAMPLER_GATHER4_PO_C 0x12
#define GEN7_MSG_SAMPLER_SAMPLE_D_C 0x14
#define GEN7_MSG_SAMPLER_SAMPLE_LZ 0x18
#define GEN7_MSG_SAMPLER_SAMPLE_C_LC 0x19
#define GEN7_MSG_SAMPLER_SAMPLE_LD_LZ 0x1a
#define GEN7_MSG_SAMPLER_LD_MCS 0x1d
#define GEN7_MSG_SAMPLER_LD2DMS 0x1e
#define GEN7_MSG_SAMPLER_LD2DSS 0x1f
#define GEN6_MSG_DP_OWORD_BLOCK_READ 0x0
#define GEN6_MSG_DP_RT_UNORM_READ 0x1
#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ 0x2
#define GEN6_MSG_DP_MEDIA_BLOCK_READ 0x4
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_READ 0x5
#define GEN6_MSG_DP_DWORD_SCATTERED_READ 0x6
#define GEN6_MSG_DP_DWORD_ATOMIC_WRITE 0x7
#define GEN6_MSG_DP_OWORD_BLOCK_WRITE 0x8
#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_WRITE 0x9
#define GEN6_MSG_DP_MEDIA_BLOCK_WRITE 0xa
#define GEN6_MSG_DP_DWORD_SCATTERED_WRITE 0xb
#define GEN6_MSG_DP_RT_WRITE 0xc
#define GEN6_MSG_DP_SVB_WRITE 0xd
#define GEN6_MSG_DP_RT_UNORM_WRITE 0xe
#define GEN7_MSG_DP_SAMPLER_OWORD_BLOCK_READ 0x1
#define GEN7_MSG_DP_SAMPLER_MEDIA_BLOCK_READ 0x4
#define GEN7_MSG_DP_RC_MEDIA_BLOCK_READ 0x4
#define GEN7_MSG_DP_RC_TYPED_SURFACE_READ 0x5
#define GEN7_MSG_DP_RC_TYPED_ATOMIC_OP 0x6
#define GEN7_MSG_DP_RC_MEMORY_FENCE 0x7
#define GEN7_MSG_DP_RC_MEDIA_BLOCK_WRITE 0xa
#define GEN7_MSG_DP_RC_RT_WRITE 0xc
#define GEN7_MSG_DP_RC_TYPED_SURFACE_WRITE 0xd
#define GEN7_MSG_DP_CC_OWORD_BLOCK_READ 0x0
#define GEN7_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ 0x1
#define GEN7_MSG_DP_CC_OWORD_DUAL_BLOCK_READ 0x2
#define GEN7_MSG_DP_CC_DWORD_SCATTERED_READ 0x3
#define GEN7_MSG_DP_DC0_OWORD_BLOCK_READ 0x0
#define GEN7_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ 0x1
#define GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ 0x2
#define GEN7_MSG_DP_DC0_DWORD_SCATTERED_READ 0x3
#define GEN7_MSG_DP_DC0_BYTE_SCATTERED_READ 0x4
#define GEN7_MSG_DP_DC0_UNTYPED_SURFACE_READ 0x5
#define GEN7_MSG_DP_DC0_UNTYPED_ATOMIC_OP 0x6
#define GEN7_MSG_DP_DC0_MEMORY_FENCE 0x7
#define GEN7_MSG_DP_DC0_OWORD_BLOCK_WRITE 0x8
#define GEN7_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE 0xa
#define GEN7_MSG_DP_DC0_DWORD_SCATTERED_WRITE 0xb
#define GEN7_MSG_DP_DC0_BYTE_SCATTERED_WRITE 0xc
#define GEN7_MSG_DP_DC0_UNTYPED_SURFACE_WRITE 0xd
#define GEN75_MSG_DP_SAMPLER_READ_SURFACE_INFO 0x0
#define GEN75_MSG_DP_SAMPLER_UNALIGNED_OWORD_BLOCK_READ 0x1
#define GEN75_MSG_DP_SAMPLER_MEDIA_BLOCK_READ 0x4
#define GEN75_MSG_DP_RC_MEDIA_BLOCK_READ 0x4
#define GEN75_MSG_DP_RC_MEMORY_FENCE 0x7
#define GEN75_MSG_DP_RC_MEDIA_BLOCK_WRITE 0xa
#define GEN75_MSG_DP_RC_RT_WRITE 0xc
#define GEN75_MSG_DP_CC_OWORD_BLOCK_READ 0x0
#define GEN75_MSG_DP_CC_UNALIGNED_OWORD_BLOCK_READ 0x1
#define GEN75_MSG_DP_CC_OWORD_DUAL_BLOCK_READ 0x2
#define GEN75_MSG_DP_CC_DWORD_SCATTERED_READ 0x3
#define GEN75_MSG_DP_DC0_OWORD_BLOCK_READ 0x0
#define GEN75_MSG_DP_DC0_UNALIGNED_OWORD_BLOCK_READ 0x1
#define GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_READ 0x2
#define GEN75_MSG_DP_DC0_DWORD_SCATTERED_READ 0x3
#define GEN75_MSG_DP_DC0_BYTE_SCATTERED_READ 0x4
#define GEN75_MSG_DP_DC0_MEMORY_FENCE 0x7
#define GEN75_MSG_DP_DC0_OWORD_BLOCK_WRITE 0x8
#define GEN75_MSG_DP_DC0_OWORD_DUAL_BLOCK_WRITE 0xa
#define GEN75_MSG_DP_DC0_DWORD_SCATTERED_WRITE 0xb
#define GEN75_MSG_DP_DC0_BYTE_SCATTERED_WRITE 0xc
#define GEN75_MSG_DP_DC1_UNTYPED_SURFACE_READ 0x1
#define GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP 0x2
#define GEN75_MSG_DP_DC1_UNTYPED_ATOMIC_OP_SIMD4X2 0x3
#define GEN75_MSG_DP_DC1_MEDIA_BLOCK_READ 0x4
#define GEN75_MSG_DP_DC1_TYPED_SURFACE_READ 0x5
#define GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP 0x6
#define GEN75_MSG_DP_DC1_TYPED_ATOMIC_OP_SIMD4X2 0x7
#define GEN75_MSG_DP_DC1_UNTYPED_SURFACE_WRITE 0x9
#define GEN75_MSG_DP_DC1_MEDIA_BLOCK_WRITE 0xa
#define GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP 0xb
#define GEN75_MSG_DP_DC1_ATOMIC_COUNTER_OP_SIMD4X2 0xc
#define GEN75_MSG_DP_DC1_TYPED_SURFACE_WRITE 0xd
#define GEN6_MSG_EOT (0x1 << 31)
#define GEN6_MSG_MLEN__MASK 0x1e000000
#define GEN6_MSG_MLEN__SHIFT 25
#define GEN6_MSG_RLEN__MASK 0x01f00000
#define GEN6_MSG_RLEN__SHIFT 20
#define GEN6_MSG_HEADER_PRESENT (0x1 << 19)
#define GEN6_MSG_FUNCTION_CONTROL__MASK 0x0007ffff
#define GEN6_MSG_FUNCTION_CONTROL__SHIFT 0
#define GEN6_MSG_URB_COMPLETE (0x1 << 15)
#define GEN6_MSG_URB_USED (0x1 << 14)
#define GEN6_MSG_URB_ALLOCATE (0x1 << 13)
#define GEN6_MSG_URB_INTERLEAVED (0x1 << 10)
#define GEN6_MSG_URB_OFFSET__MASK 0x000003f0
#define GEN6_MSG_URB_OFFSET__SHIFT 4
#define GEN6_MSG_URB_OP__MASK 0x0000000f
#define GEN6_MSG_URB_OP__SHIFT 0
#define GEN7_MSG_URB_PER_SLOT_OFFSET (0x1 << 16)
#define GEN7_MSG_URB_COMPLETE (0x1 << 15)
#define GEN7_MSG_URB_INTERLEAVED (0x1 << 14)
#define GEN7_MSG_URB_GLOBAL_OFFSET__MASK 0x00003ff8
#define GEN7_MSG_URB_GLOBAL_OFFSET__SHIFT 3
#define GEN7_MSG_URB_OP__MASK 0x00000007
#define GEN7_MSG_URB_OP__SHIFT 0
#define GEN6_MSG_SAMPLER_SIMD__MASK 0x00030000
#define GEN6_MSG_SAMPLER_SIMD__SHIFT 16
#define GEN6_MSG_SAMPLER_OP__MASK 0x0000f000
#define GEN6_MSG_SAMPLER_OP__SHIFT 12
#define GEN7_MSG_SAMPLER_SIMD__MASK 0x00060000
#define GEN7_MSG_SAMPLER_SIMD__SHIFT 17
#define GEN7_MSG_SAMPLER_OP__MASK 0x0001f000
#define GEN7_MSG_SAMPLER_OP__SHIFT 12
#define GEN6_MSG_SAMPLER_INDEX__MASK 0x00000f00
#define GEN6_MSG_SAMPLER_INDEX__SHIFT 8
#define GEN6_MSG_SAMPLER_SURFACE__MASK 0x000000ff
#define GEN6_MSG_SAMPLER_SURFACE__SHIFT 0
#define GEN6_MSG_DP_SEND_WRITE_COMMIT (0x1 << 17)
#define GEN6_MSG_DP_OP__MASK 0x0001e000
#define GEN6_MSG_DP_OP__SHIFT 13
#define GEN7_MSG_DP_CATEGORY (0x1 << 18)
#define GEN7_MSG_DP_OP__MASK 0x0003c000
#define GEN7_MSG_DP_OP__SHIFT 14
#define GEN7_MSG_DP_OWORD_BLOCK_READ_INVALIDATE (0x1 << 13)
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__MASK 0x00000700
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE__SHIFT 8
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO (0x0 << 8)
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_HI (0x1 << 8)
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_2 (0x2 << 8)
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_4 (0x3 << 8)
#define GEN6_MSG_DP_OWORD_BLOCK_SIZE_8 (0x4 << 8)
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__MASK 0x00000700
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE__SHIFT 8
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_LO (0x0 << 8)
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_1_HI (0x1 << 8)
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_2 (0x2 << 8)
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_4 (0x3 << 8)
#define GEN6_MSG_DP_UNALIGNED_OWORD_BLOCK_SIZE_8 (0x4 << 8)
#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__MASK 0x00000300
#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE__SHIFT 8
#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1 (0x0 << 8)
#define GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_4 (0x2 << 8)
#define GEN7_MSG_DP_DWORD_SCATTERED_READ_INVALIDATE (0x1 << 13)
#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE__MASK 0x00000300
#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE__SHIFT 8
#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_8 (0x2 << 8)
#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_16 (0x3 << 8)
#define GEN6_MSG_DP_RT_LAST (0x1 << 12)
#define GEN6_MSG_DP_RT_MODE__MASK 0x00000700
#define GEN6_MSG_DP_RT_MODE__SHIFT 8
#define GEN6_MSG_DP_RT_MODE_SIMD16 (0x0 << 8)
#define GEN6_MSG_DP_RT_MODE_SIMD16_REPDATA (0x1 << 8)
#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_LO (0x2 << 8)
#define GEN6_MSG_DP_RT_MODE_SIMD8_DUALSRC_HI (0x3 << 8)
#define GEN6_MSG_DP_RT_MODE_SIMD8_LO (0x4 << 8)
#define GEN6_MSG_DP_RT_MODE_SIMD8_IMAGE_WR (0x5 << 8)
#define GEN6_MSG_DP_SURFACE__MASK 0x000000ff
#define GEN6_MSG_DP_SURFACE__SHIFT 0
#endif /* GEN_EU_MESSAGE_XML */

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#ifndef GEN_MI_XML
#define GEN_MI_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_MI_TYPE__MASK 0xe0000000
#define GEN6_MI_TYPE__SHIFT 29
#define GEN6_MI_TYPE_MI (0x0 << 29)
#define GEN6_MI_OPCODE__MASK 0x1f800000
#define GEN6_MI_OPCODE__SHIFT 23
#define GEN6_MI_OPCODE_MI_NOOP (0x0 << 23)
#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END (0xa << 23)
#define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23)
#define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23)
#define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23)
#define GEN6_MI_OPCODE_MI_FLUSH_DW (0x26 << 23)
#define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23)
#define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23)
#define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23)
#define GEN6_MI_LENGTH__MASK 0x0000003f
#define GEN6_MI_LENGTH__SHIFT 0
#define GEN6_MI_NOOP__SIZE 1
#define GEN6_MI_BATCH_BUFFER_END__SIZE 1
#define GEN6_MI_STORE_DATA_IMM__SIZE 5
#define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22)
#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc
#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT 2
#define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR 2
#define GEN6_MI_LOAD_REGISTER_IMM__SIZE 3
#define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK 0x00000f00
#define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT 8
#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK 0x007ffffc
#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT 2
#define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR 2
#define GEN6_MI_STORE_REGISTER_MEM__SIZE 3
#define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22)
#define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE (0x1 << 21)
#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK 0x007ffffc
#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT 2
#define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR 2
#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc
#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT 2
#define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2
#define GEN6_MI_FLUSH_DW__SIZE 4
#define GEN6_MI_REPORT_PERF_COUNT__SIZE 3
#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK 0xffffffc0
#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT 6
#define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR 6
#define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4)
#define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0)
#define GEN7_MI_LOAD_REGISTER_MEM__SIZE 3
#define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22)
#define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE (0x1 << 21)
#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK 0x007ffffc
#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT 2
#define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR 2
#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc
#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT 2
#define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR 2
#define GEN6_MI_BATCH_BUFFER_START__SIZE 2
#define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22)
#define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16)
#define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15)
#define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13)
#define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11)
#define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8)
#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc
#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT 2
#define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR 2
#endif /* GEN_MI_XML */

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#ifndef GEN_REGS_XML
#define GEN_REGS_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_REG_MASK__MASK 0xffff0000
#define GEN6_REG_MASK__SHIFT 16
#define GEN6_REG__SIZE 0x400000
#define GEN6_REG_HS_INVOCATION_COUNT 0x2300
#define GEN6_REG_DS_INVOCATION_COUNT 0x2308
#define GEN6_REG_IA_VERTICES_COUNT 0x2310
#define GEN6_REG_IA_PRIMITIVES_COUNT 0x2318
#define GEN6_REG_VS_INVOCATION_COUNT 0x2320
#define GEN6_REG_GS_INVOCATION_COUNT 0x2328
#define GEN6_REG_GS_PRIMITIVES_COUNT 0x2330
#define GEN6_REG_CL_INVOCATION_COUNT 0x2338
#define GEN6_REG_CL_PRIMITIVES_COUNT 0x2340
#define GEN6_REG_PS_INVOCATION_COUNT 0x2348
#define GEN6_REG_TIMESTAMP 0x2358
#define GEN6_REG_BCS_SWCTRL 0x22200
#define GEN6_REG_BCS_SWCTRL_DST_TILING_Y (0x1 << 1)
#define GEN6_REG_BCS_SWCTRL_SRC_TILING_Y (0x1 << 0)
#endif /* GEN_REGS_XML */

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#ifndef GEN_RENDER_DYNAMIC_XML
#define GEN_RENDER_DYNAMIC_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_COMPAREFUNCTION_ALWAYS 0x0
#define GEN6_COMPAREFUNCTION_NEVER 0x1
#define GEN6_COMPAREFUNCTION_LESS 0x2
#define GEN6_COMPAREFUNCTION_EQUAL 0x3
#define GEN6_COMPAREFUNCTION_LEQUAL 0x4
#define GEN6_COMPAREFUNCTION_GREATER 0x5
#define GEN6_COMPAREFUNCTION_NOTEQUAL 0x6
#define GEN6_COMPAREFUNCTION_GEQUAL 0x7
#define GEN6_STENCILOP_KEEP 0x0
#define GEN6_STENCILOP_ZERO 0x1
#define GEN6_STENCILOP_REPLACE 0x2
#define GEN6_STENCILOP_INCRSAT 0x3
#define GEN6_STENCILOP_DECRSAT 0x4
#define GEN6_STENCILOP_INCR 0x5
#define GEN6_STENCILOP_DECR 0x6
#define GEN6_STENCILOP_INVERT 0x7
#define GEN6_BLENDFACTOR_ONE 0x1
#define GEN6_BLENDFACTOR_SRC_COLOR 0x2
#define GEN6_BLENDFACTOR_SRC_ALPHA 0x3
#define GEN6_BLENDFACTOR_DST_ALPHA 0x4
#define GEN6_BLENDFACTOR_DST_COLOR 0x5
#define GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
#define GEN6_BLENDFACTOR_CONST_COLOR 0x7
#define GEN6_BLENDFACTOR_CONST_ALPHA 0x8
#define GEN6_BLENDFACTOR_SRC1_COLOR 0x9
#define GEN6_BLENDFACTOR_SRC1_ALPHA 0xa
#define GEN6_BLENDFACTOR_ZERO 0x11
#define GEN6_BLENDFACTOR_INV_SRC_COLOR 0x12
#define GEN6_BLENDFACTOR_INV_SRC_ALPHA 0x13
#define GEN6_BLENDFACTOR_INV_DST_ALPHA 0x14
#define GEN6_BLENDFACTOR_INV_DST_COLOR 0x15
#define GEN6_BLENDFACTOR_INV_CONST_COLOR 0x17
#define GEN6_BLENDFACTOR_INV_CONST_ALPHA 0x18
#define GEN6_BLENDFACTOR_INV_SRC1_COLOR 0x19
#define GEN6_BLENDFACTOR_INV_SRC1_ALPHA 0x1a
#define GEN6_BLENDFUNCTION_ADD 0x0
#define GEN6_BLENDFUNCTION_SUBTRACT 0x1
#define GEN6_BLENDFUNCTION_REVERSE_SUBTRACT 0x2
#define GEN6_BLENDFUNCTION_MIN 0x3
#define GEN6_BLENDFUNCTION_MAX 0x4
#define GEN6_LOGICOP_CLEAR 0x0
#define GEN6_LOGICOP_NOR 0x1
#define GEN6_LOGICOP_AND_INVERTED 0x2
#define GEN6_LOGICOP_COPY_INVERTED 0x3
#define GEN6_LOGICOP_AND_REVERSE 0x4
#define GEN6_LOGICOP_INVERT 0x5
#define GEN6_LOGICOP_XOR 0x6
#define GEN6_LOGICOP_NAND 0x7
#define GEN6_LOGICOP_AND 0x8
#define GEN6_LOGICOP_EQUIV 0x9
#define GEN6_LOGICOP_NOOP 0xa
#define GEN6_LOGICOP_OR_INVERTED 0xb
#define GEN6_LOGICOP_COPY 0xc
#define GEN6_LOGICOP_OR_REVERSE 0xd
#define GEN6_LOGICOP_OR 0xe
#define GEN6_LOGICOP_SET 0xf
#define GEN6_MIPFILTER_NONE 0x0
#define GEN6_MIPFILTER_NEAREST 0x1
#define GEN6_MIPFILTER_LINEAR 0x3
#define GEN6_MAPFILTER_NEAREST 0x0
#define GEN6_MAPFILTER_LINEAR 0x1
#define GEN6_MAPFILTER_ANISOTROPIC 0x2
#define GEN6_MAPFILTER_MONO 0x6
#define GEN6_ANISORATIO_2 0x0
#define GEN6_ANISORATIO_4 0x1
#define GEN6_ANISORATIO_6 0x2
#define GEN6_ANISORATIO_8 0x3
#define GEN6_ANISORATIO_10 0x4
#define GEN6_ANISORATIO_12 0x5
#define GEN6_ANISORATIO_14 0x6
#define GEN6_ANISORATIO_16 0x7
#define GEN6_TEXCOORDMODE_WRAP 0x0
#define GEN6_TEXCOORDMODE_MIRROR 0x1
#define GEN6_TEXCOORDMODE_CLAMP 0x2
#define GEN6_TEXCOORDMODE_CUBE 0x3
#define GEN6_TEXCOORDMODE_CLAMP_BORDER 0x4
#define GEN6_TEXCOORDMODE_MIRROR_ONCE 0x5
#define GEN6_KEYFILTER_KILL_ON_ANY_MATCH 0x0
#define GEN6_KEYFILTER_REPLACE_BLACK 0x1
#define GEN6_COLOR_CALC_STATE__SIZE 6
#define GEN6_CC_DW0_STENCIL0_REF__MASK 0xff000000
#define GEN6_CC_DW0_STENCIL0_REF__SHIFT 24
#define GEN6_CC_DW0_STENCIL1_REF__MASK 0x00ff0000
#define GEN6_CC_DW0_STENCIL1_REF__SHIFT 16
#define GEN6_CC_DW0_ROUND_DISABLE_DISABLE (0x1 << 15)
#define GEN6_CC_DW0_ALPHATEST__MASK 0x00000001
#define GEN6_CC_DW0_ALPHATEST__SHIFT 0
#define GEN6_CC_DW0_ALPHATEST_UNORM8 0x0
#define GEN6_CC_DW0_ALPHATEST_FLOAT32 0x1
#define GEN6_DEPTH_STENCIL_STATE__SIZE 3
#define GEN6_ZS_DW0_STENCIL_TEST_ENABLE (0x1 << 31)
#define GEN6_ZS_DW0_STENCIL0_FUNC__MASK 0x70000000
#define GEN6_ZS_DW0_STENCIL0_FUNC__SHIFT 28
#define GEN6_ZS_DW0_STENCIL0_FAIL_OP__MASK 0x0e000000
#define GEN6_ZS_DW0_STENCIL0_FAIL_OP__SHIFT 25
#define GEN6_ZS_DW0_STENCIL0_ZFAIL_OP__MASK 0x01c00000
#define GEN6_ZS_DW0_STENCIL0_ZFAIL_OP__SHIFT 22
#define GEN6_ZS_DW0_STENCIL0_ZPASS_OP__MASK 0x00380000
#define GEN6_ZS_DW0_STENCIL0_ZPASS_OP__SHIFT 19
#define GEN6_ZS_DW0_STENCIL_WRITE_ENABLE (0x1 << 18)
#define GEN6_ZS_DW0_STENCIL1_ENABLE (0x1 << 15)
#define GEN6_ZS_DW0_STENCIL1_FUNC__MASK 0x00007000
#define GEN6_ZS_DW0_STENCIL1_FUNC__SHIFT 12
#define GEN6_ZS_DW0_STENCIL1_FAIL_OP__MASK 0x00000e00
#define GEN6_ZS_DW0_STENCIL1_FAIL_OP__SHIFT 9
#define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__MASK 0x000001c0
#define GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__SHIFT 6
#define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__MASK 0x00000038
#define GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT 3
#define GEN6_ZS_DW1_STENCIL0_VALUEMASK__MASK 0xff000000
#define GEN6_ZS_DW1_STENCIL0_VALUEMASK__SHIFT 24
#define GEN6_ZS_DW1_STENCIL0_WRITEMASK__MASK 0x00ff0000
#define GEN6_ZS_DW1_STENCIL0_WRITEMASK__SHIFT 16
#define GEN6_ZS_DW1_STENCIL1_VALUEMASK__MASK 0x0000ff00
#define GEN6_ZS_DW1_STENCIL1_VALUEMASK__SHIFT 8
#define GEN6_ZS_DW1_STENCIL1_WRITEMASK__MASK 0x000000ff
#define GEN6_ZS_DW1_STENCIL1_WRITEMASK__SHIFT 0
#define GEN6_ZS_DW2_DEPTH_TEST_ENABLE (0x1 << 31)
#define GEN6_ZS_DW2_DEPTH_FUNC__MASK 0x38000000
#define GEN6_ZS_DW2_DEPTH_FUNC__SHIFT 27
#define GEN6_ZS_DW2_DEPTH_WRITE_ENABLE (0x1 << 26)
#define GEN6_BLEND_STATE__SIZE 2
#define GEN6_BLEND_DW0_BLEND_ENABLE (0x1 << 31)
#define GEN6_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE (0x1 << 30)
#define GEN6_BLEND_DW0_ALPHA_FUNC__MASK 0x1c000000
#define GEN6_BLEND_DW0_ALPHA_FUNC__SHIFT 26
#define GEN6_BLEND_DW0_SRC_ALPHA_FACTOR__MASK 0x01f00000
#define GEN6_BLEND_DW0_SRC_ALPHA_FACTOR__SHIFT 20
#define GEN6_BLEND_DW0_DST_ALPHA_FACTOR__MASK 0x000f8000
#define GEN6_BLEND_DW0_DST_ALPHA_FACTOR__SHIFT 15
#define GEN6_BLEND_DW0_COLOR_FUNC__MASK 0x00003800
#define GEN6_BLEND_DW0_COLOR_FUNC__SHIFT 11
#define GEN6_BLEND_DW0_SRC_COLOR_FACTOR__MASK 0x000003e0
#define GEN6_BLEND_DW0_SRC_COLOR_FACTOR__SHIFT 5
#define GEN6_BLEND_DW0_DST_COLOR_FACTOR__MASK 0x0000001f
#define GEN6_BLEND_DW0_DST_COLOR_FACTOR__SHIFT 0
#define GEN6_BLEND_DW1_ALPHA_TO_COVERAGE (0x1 << 31)
#define GEN6_BLEND_DW1_ALPHA_TO_ONE (0x1 << 30)
#define GEN6_BLEND_DW1_ALPHA_TO_COVERAGE_DITHER (0x1 << 29)
#define GEN6_BLEND_DW1_WRITE_DISABLE_A (0x1 << 27)
#define GEN6_BLEND_DW1_WRITE_DISABLE_R (0x1 << 26)
#define GEN6_BLEND_DW1_WRITE_DISABLE_G (0x1 << 25)
#define GEN6_BLEND_DW1_WRITE_DISABLE_B (0x1 << 24)
#define GEN6_BLEND_DW1_LOGICOP_ENABLE (0x1 << 22)
#define GEN6_BLEND_DW1_LOGICOP_FUNC__MASK 0x003c0000
#define GEN6_BLEND_DW1_LOGICOP_FUNC__SHIFT 18
#define GEN6_BLEND_DW1_ALPHA_TEST_ENABLE (0x1 << 16)
#define GEN6_BLEND_DW1_ALPHA_TEST_FUNC__MASK 0x0000e000
#define GEN6_BLEND_DW1_ALPHA_TEST_FUNC__SHIFT 13
#define GEN6_BLEND_DW1_DITHER_ENABLE (0x1 << 12)
#define GEN6_BLEND_DW1_X_DITHER_OFFSET__MASK 0x00000c00
#define GEN6_BLEND_DW1_X_DITHER_OFFSET__SHIFT 10
#define GEN6_BLEND_DW1_Y_DITHER_OFFSET__MASK 0x00000300
#define GEN6_BLEND_DW1_Y_DITHER_OFFSET__SHIFT 8
#define GEN6_BLEND_DW1_COLORCLAMP__MASK 0x0000000c
#define GEN6_BLEND_DW1_COLORCLAMP__SHIFT 2
#define GEN6_BLEND_DW1_COLORCLAMP_UNORM (0x0 << 2)
#define GEN6_BLEND_DW1_COLORCLAMP_SNORM (0x1 << 2)
#define GEN6_BLEND_DW1_COLORCLAMP_RTFORMAT (0x2 << 2)
#define GEN6_BLEND_DW1_PRE_BLEND_CLAMP (0x1 << 1)
#define GEN6_BLEND_DW1_POST_BLEND_CLAMP (0x1 << 0)
#define GEN6_CLIP_VIEWPORT__SIZE 4
#define GEN6_SF_VIEWPORT__SIZE 8
#define GEN7_SF_CLIP_VIEWPORT__SIZE 16
#define GEN6_CC_VIEWPORT__SIZE 2
#define GEN6_SCISSOR_RECT__SIZE 2
#define GEN6_SCISSOR_DW0_MIN_Y__MASK 0xffff0000
#define GEN6_SCISSOR_DW0_MIN_Y__SHIFT 16
#define GEN6_SCISSOR_DW0_MIN_X__MASK 0x0000ffff
#define GEN6_SCISSOR_DW0_MIN_X__SHIFT 0
#define GEN6_SCISSOR_DW1_MAX_Y__MASK 0xffff0000
#define GEN6_SCISSOR_DW1_MAX_Y__SHIFT 16
#define GEN6_SCISSOR_DW1_MAX_X__MASK 0x0000ffff
#define GEN6_SCISSOR_DW1_MAX_X__SHIFT 0
#define GEN6_SAMPLER_BORDER_COLOR__SIZE 12
#define GEN6_SAMPLER_STATE__SIZE 4
#define GEN6_SAMPLER_DW0_DISABLE (0x1 << 31)
#define GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28)
#define GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL (0x1 << 27)
#define GEN6_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000
#define GEN6_SAMPLER_DW0_BASE_LOD__SHIFT 22
#define GEN6_SAMPLER_DW0_MIP_FILTER__MASK 0x00300000
#define GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT 20
#define GEN6_SAMPLER_DW0_MAG_FILTER__MASK 0x000e0000
#define GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT 17
#define GEN6_SAMPLER_DW0_MIN_FILTER__MASK 0x0001c000
#define GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT 14
#define GEN6_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ff8
#define GEN6_SAMPLER_DW0_LOD_BIAS__SHIFT 3
#define GEN6_SAMPLER_DW0_LOD_BIAS__RADIX 6
#define GEN6_SAMPLER_DW0_SHADOW_FUNC__MASK 0x00000007
#define GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT 0
#define GEN6_SAMPLER_DW1_MIN_LOD__MASK 0xffc00000
#define GEN6_SAMPLER_DW1_MIN_LOD__SHIFT 22
#define GEN6_SAMPLER_DW1_MIN_LOD__RADIX 6
#define GEN6_SAMPLER_DW1_MAX_LOD__MASK 0x003ff000
#define GEN6_SAMPLER_DW1_MAX_LOD__SHIFT 12
#define GEN6_SAMPLER_DW1_MAX_LOD__RADIX 6
#define GEN6_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000200
#define GEN6_SAMPLER_DW1_CUBECTRLMODE__SHIFT 9
#define GEN6_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED (0x0 << 9)
#define GEN6_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE (0x1 << 9)
#define GEN6_SAMPLER_DW1_U_WRAP__MASK 0x000001c0
#define GEN6_SAMPLER_DW1_U_WRAP__SHIFT 6
#define GEN6_SAMPLER_DW1_V_WRAP__MASK 0x00000038
#define GEN6_SAMPLER_DW1_V_WRAP__SHIFT 3
#define GEN6_SAMPLER_DW1_R_WRAP__MASK 0x00000007
#define GEN6_SAMPLER_DW1_R_WRAP__SHIFT 0
#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK 0xffffffe0
#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5
#define GEN6_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5
#define GEN6_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25)
#define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000
#define GEN6_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23
#define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__MASK 0x00400000
#define GEN6_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT 22
#define GEN6_SAMPLER_DW3_MAX_ANISO__MASK 0x00380000
#define GEN6_SAMPLER_DW3_MAX_ANISO__SHIFT 19
#define GEN6_SAMPLER_DW3_U_MAG_ROUND (0x1 << 18)
#define GEN6_SAMPLER_DW3_U_MIN_ROUND (0x1 << 17)
#define GEN6_SAMPLER_DW3_V_MAG_ROUND (0x1 << 16)
#define GEN6_SAMPLER_DW3_V_MIN_ROUND (0x1 << 15)
#define GEN6_SAMPLER_DW3_R_MAG_ROUND (0x1 << 14)
#define GEN6_SAMPLER_DW3_R_MIN_ROUND (0x1 << 13)
#define GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 0)
#define GEN7_SAMPLER_DW0_DISABLE (0x1 << 31)
#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__MASK 0x20000000
#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE__SHIFT 29
#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL (0x0 << 29)
#define GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX9 (0x1 << 29)
#define GEN7_SAMPLER_DW0_LOD_PRECLAMP_ENABLE (0x1 << 28)
#define GEN7_SAMPLER_DW0_BASE_LOD__MASK 0x07c00000
#define GEN7_SAMPLER_DW0_BASE_LOD__SHIFT 22
#define GEN7_SAMPLER_DW0_MIP_FILTER__MASK 0x00300000
#define GEN7_SAMPLER_DW0_MIP_FILTER__SHIFT 20
#define GEN7_SAMPLER_DW0_MAG_FILTER__MASK 0x000e0000
#define GEN7_SAMPLER_DW0_MAG_FILTER__SHIFT 17
#define GEN7_SAMPLER_DW0_MIN_FILTER__MASK 0x0001c000
#define GEN7_SAMPLER_DW0_MIN_FILTER__SHIFT 14
#define GEN7_SAMPLER_DW0_LOD_BIAS__MASK 0x00003ffe
#define GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT 1
#define GEN7_SAMPLER_DW0_LOD_BIAS__RADIX 8
#define GEN7_SAMPLER_DW0_ANISO_ALGO__MASK 0x00000001
#define GEN7_SAMPLER_DW0_ANISO_ALGO__SHIFT 0
#define GEN7_SAMPLER_DW0_ANISO_ALGO_LEGACY 0x0
#define GEN7_SAMPLER_DW0_ANISO_ALGO_EWA 0x1
#define GEN7_SAMPLER_DW1_MIN_LOD__MASK 0xfff00000
#define GEN7_SAMPLER_DW1_MIN_LOD__SHIFT 20
#define GEN7_SAMPLER_DW1_MIN_LOD__RADIX 8
#define GEN7_SAMPLER_DW1_MAX_LOD__MASK 0x000fff00
#define GEN7_SAMPLER_DW1_MAX_LOD__SHIFT 8
#define GEN7_SAMPLER_DW1_MAX_LOD__RADIX 8
#define GEN7_SAMPLER_DW1_SHADOW_FUNC__MASK 0x0000000e
#define GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT 1
#define GEN7_SAMPLER_DW1_CUBECTRLMODE__MASK 0x00000001
#define GEN7_SAMPLER_DW1_CUBECTRLMODE__SHIFT 0
#define GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED 0x0
#define GEN7_SAMPLER_DW1_CUBECTRLMODE_OVERRIDE 0x1
#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__MASK 0xffffffe0
#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__SHIFT 5
#define GEN7_SAMPLER_DW2_BORDER_COLOR_ADDR__SHR 5
#define GEN7_SAMPLER_DW3_CHROMAKEY_ENABLE (0x1 << 25)
#define GEN7_SAMPLER_DW3_CHROMAKEY_INDEX__MASK 0x01800000
#define GEN7_SAMPLER_DW3_CHROMAKEY_INDEX__SHIFT 23
#define GEN7_SAMPLER_DW3_CHROMAKEY_MODE__MASK 0x00400000
#define GEN7_SAMPLER_DW3_CHROMAKEY_MODE__SHIFT 22
#define GEN7_SAMPLER_DW3_MAX_ANISO__MASK 0x00380000
#define GEN7_SAMPLER_DW3_MAX_ANISO__SHIFT 19
#define GEN7_SAMPLER_DW3_U_MAG_ROUND (0x1 << 18)
#define GEN7_SAMPLER_DW3_U_MIN_ROUND (0x1 << 17)
#define GEN7_SAMPLER_DW3_V_MAG_ROUND (0x1 << 16)
#define GEN7_SAMPLER_DW3_V_MIN_ROUND (0x1 << 15)
#define GEN7_SAMPLER_DW3_R_MAG_ROUND (0x1 << 14)
#define GEN7_SAMPLER_DW3_R_MIN_ROUND (0x1 << 13)
#define GEN7_SAMPLER_DW3_TRIQUAL__MASK 0x00001800
#define GEN7_SAMPLER_DW3_TRIQUAL__SHIFT 11
#define GEN7_SAMPLER_DW3_TRIQUAL_FULL (0x0 << 11)
#define GEN75_SAMPLER_DW3_TRIQUAL_HIGH (0x1 << 11)
#define GEN7_SAMPLER_DW3_TRIQUAL_MED (0x2 << 11)
#define GEN7_SAMPLER_DW3_TRIQUAL_LOW (0x3 << 11)
#define GEN7_SAMPLER_DW3_NON_NORMALIZED_COORD (0x1 << 10)
#define GEN7_SAMPLER_DW3_U_WRAP__MASK 0x000001c0
#define GEN7_SAMPLER_DW3_U_WRAP__SHIFT 6
#define GEN7_SAMPLER_DW3_V_WRAP__MASK 0x00000038
#define GEN7_SAMPLER_DW3_V_WRAP__SHIFT 3
#define GEN7_SAMPLER_DW3_R_WRAP__MASK 0x00000007
#define GEN7_SAMPLER_DW3_R_WRAP__SHIFT 0
#endif /* GEN_RENDER_DYNAMIC_XML */

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#ifndef GEN_RENDER_SURFACE_XML
#define GEN_RENDER_SURFACE_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
https://github.com/olvaffe/envytools/
git clone https://github.com/olvaffe/envytools.git
Copyright (C) 2014 by the following authors:
- Chia-I Wu <olvaffe@gmail.com> (olv)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define GEN6_FORMAT_R32G32B32A32_FLOAT 0x0
#define GEN6_FORMAT_R32G32B32A32_SINT 0x1
#define GEN6_FORMAT_R32G32B32A32_UINT 0x2
#define GEN6_FORMAT_R32G32B32A32_UNORM 0x3
#define GEN6_FORMAT_R32G32B32A32_SNORM 0x4
#define GEN6_FORMAT_R64G64_FLOAT 0x5
#define GEN6_FORMAT_R32G32B32X32_FLOAT 0x6
#define GEN6_FORMAT_R32G32B32A32_SSCALED 0x7
#define GEN6_FORMAT_R32G32B32A32_USCALED 0x8
#define GEN6_FORMAT_R32G32B32A32_SFIXED 0x20
#define GEN6_FORMAT_R64G64_PASSTHRU 0x21
#define GEN6_FORMAT_R32G32B32_FLOAT 0x40
#define GEN6_FORMAT_R32G32B32_SINT 0x41
#define GEN6_FORMAT_R32G32B32_UINT 0x42
#define GEN6_FORMAT_R32G32B32_UNORM 0x43
#define GEN6_FORMAT_R32G32B32_SNORM 0x44
#define GEN6_FORMAT_R32G32B32_SSCALED 0x45
#define GEN6_FORMAT_R32G32B32_USCALED 0x46
#define GEN6_FORMAT_R32G32B32_SFIXED 0x50
#define GEN6_FORMAT_R16G16B16A16_UNORM 0x80
#define GEN6_FORMAT_R16G16B16A16_SNORM 0x81
#define GEN6_FORMAT_R16G16B16A16_SINT 0x82
#define GEN6_FORMAT_R16G16B16A16_UINT 0x83
#define GEN6_FORMAT_R16G16B16A16_FLOAT 0x84
#define GEN6_FORMAT_R32G32_FLOAT 0x85
#define GEN6_FORMAT_R32G32_SINT 0x86
#define GEN6_FORMAT_R32G32_UINT 0x87
#define GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS 0x88
#define GEN6_FORMAT_X32_TYPELESS_G8X24_UINT 0x89
#define GEN6_FORMAT_L32A32_FLOAT 0x8a
#define GEN6_FORMAT_R32G32_UNORM 0x8b
#define GEN6_FORMAT_R32G32_SNORM 0x8c
#define GEN6_FORMAT_R64_FLOAT 0x8d
#define GEN6_FORMAT_R16G16B16X16_UNORM 0x8e
#define GEN6_FORMAT_R16G16B16X16_FLOAT 0x8f
#define GEN6_FORMAT_A32X32_FLOAT 0x90
#define GEN6_FORMAT_L32X32_FLOAT 0x91
#define GEN6_FORMAT_I32X32_FLOAT 0x92
#define GEN6_FORMAT_R16G16B16A16_SSCALED 0x93
#define GEN6_FORMAT_R16G16B16A16_USCALED 0x94
#define GEN6_FORMAT_R32G32_SSCALED 0x95
#define GEN6_FORMAT_R32G32_USCALED 0x96
#define GEN6_FORMAT_R32G32_SFIXED 0xa0
#define GEN6_FORMAT_R64_PASSTHRU 0xa1
#define GEN6_FORMAT_B8G8R8A8_UNORM 0xc0
#define GEN6_FORMAT_B8G8R8A8_UNORM_SRGB 0xc1
#define GEN6_FORMAT_R10G10B10A2_UNORM 0xc2
#define GEN6_FORMAT_R10G10B10A2_UNORM_SRGB 0xc3
#define GEN6_FORMAT_R10G10B10A2_UINT 0xc4
#define GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM 0xc5
#define GEN6_FORMAT_R8G8B8A8_UNORM 0xc7
#define GEN6_FORMAT_R8G8B8A8_UNORM_SRGB 0xc8
#define GEN6_FORMAT_R8G8B8A8_SNORM 0xc9
#define GEN6_FORMAT_R8G8B8A8_SINT 0xca
#define GEN6_FORMAT_R8G8B8A8_UINT 0xcb
#define GEN6_FORMAT_R16G16_UNORM 0xcc
#define GEN6_FORMAT_R16G16_SNORM 0xcd
#define GEN6_FORMAT_R16G16_SINT 0xce
#define GEN6_FORMAT_R16G16_UINT 0xcf
#define GEN6_FORMAT_R16G16_FLOAT 0xd0
#define GEN6_FORMAT_B10G10R10A2_UNORM 0xd1
#define GEN6_FORMAT_B10G10R10A2_UNORM_SRGB 0xd2
#define GEN6_FORMAT_R11G11B10_FLOAT 0xd3
#define GEN6_FORMAT_R32_SINT 0xd6
#define GEN6_FORMAT_R32_UINT 0xd7
#define GEN6_FORMAT_R32_FLOAT 0xd8
#define GEN6_FORMAT_R24_UNORM_X8_TYPELESS 0xd9
#define GEN6_FORMAT_X24_TYPELESS_G8_UINT 0xda
#define GEN6_FORMAT_L32_UNORM 0xdd
#define GEN6_FORMAT_A32_UNORM 0xde
#define GEN6_FORMAT_L16A16_UNORM 0xdf
#define GEN6_FORMAT_I24X8_UNORM 0xe0
#define GEN6_FORMAT_L24X8_UNORM 0xe1
#define GEN6_FORMAT_A24X8_UNORM 0xe2
#define GEN6_FORMAT_I32_FLOAT 0xe3
#define GEN6_FORMAT_L32_FLOAT 0xe4
#define GEN6_FORMAT_A32_FLOAT 0xe5
#define GEN6_FORMAT_X8B8_UNORM_G8R8_SNORM 0xe6
#define GEN6_FORMAT_A8X8_UNORM_G8R8_SNORM 0xe7
#define GEN6_FORMAT_B8X8_UNORM_G8R8_SNORM 0xe8
#define GEN6_FORMAT_B8G8R8X8_UNORM 0xe9
#define GEN6_FORMAT_B8G8R8X8_UNORM_SRGB 0xea
#define GEN6_FORMAT_R8G8B8X8_UNORM 0xeb
#define GEN6_FORMAT_R8G8B8X8_UNORM_SRGB 0xec
#define GEN6_FORMAT_R9G9B9E5_SHAREDEXP 0xed
#define GEN6_FORMAT_B10G10R10X2_UNORM 0xee
#define GEN6_FORMAT_L16A16_FLOAT 0xf0
#define GEN6_FORMAT_R32_UNORM 0xf1
#define GEN6_FORMAT_R32_SNORM 0xf2
#define GEN6_FORMAT_R10G10B10X2_USCALED 0xf3
#define GEN6_FORMAT_R8G8B8A8_SSCALED 0xf4
#define GEN6_FORMAT_R8G8B8A8_USCALED 0xf5
#define GEN6_FORMAT_R16G16_SSCALED 0xf6
#define GEN6_FORMAT_R16G16_USCALED 0xf7
#define GEN6_FORMAT_R32_SSCALED 0xf8
#define GEN6_FORMAT_R32_USCALED 0xf9
#define GEN6_FORMAT_B5G6R5_UNORM 0x100
#define GEN6_FORMAT_B5G6R5_UNORM_SRGB 0x101
#define GEN6_FORMAT_B5G5R5A1_UNORM 0x102
#define GEN6_FORMAT_B5G5R5A1_UNORM_SRGB 0x103
#define GEN6_FORMAT_B4G4R4A4_UNORM 0x104
#define GEN6_FORMAT_B4G4R4A4_UNORM_SRGB 0x105
#define GEN6_FORMAT_R8G8_UNORM 0x106
#define GEN6_FORMAT_R8G8_SNORM 0x107
#define GEN6_FORMAT_R8G8_SINT 0x108
#define GEN6_FORMAT_R8G8_UINT 0x109
#define GEN6_FORMAT_R16_UNORM 0x10a
#define GEN6_FORMAT_R16_SNORM 0x10b
#define GEN6_FORMAT_R16_SINT 0x10c
#define GEN6_FORMAT_R16_UINT 0x10d
#define GEN6_FORMAT_R16_FLOAT 0x10e
#define GEN6_FORMAT_A8P8_UNORM_PALETTE0 0x10f
#define GEN6_FORMAT_A8P8_UNORM_PALETTE1 0x110
#define GEN6_FORMAT_I16_UNORM 0x111
#define GEN6_FORMAT_L16_UNORM 0x112
#define GEN6_FORMAT_A16_UNORM 0x113
#define GEN6_FORMAT_L8A8_UNORM 0x114
#define GEN6_FORMAT_I16_FLOAT 0x115
#define GEN6_FORMAT_L16_FLOAT 0x116
#define GEN6_FORMAT_A16_FLOAT 0x117
#define GEN6_FORMAT_L8A8_UNORM_SRGB 0x118
#define GEN6_FORMAT_R5G5_SNORM_B6_UNORM 0x119
#define GEN6_FORMAT_B5G5R5X1_UNORM 0x11a
#define GEN6_FORMAT_B5G5R5X1_UNORM_SRGB 0x11b
#define GEN6_FORMAT_R8G8_SSCALED 0x11c
#define GEN6_FORMAT_R8G8_USCALED 0x11d
#define GEN6_FORMAT_R16_SSCALED 0x11e
#define GEN6_FORMAT_R16_USCALED 0x11f
#define GEN6_FORMAT_P8A8_UNORM_PALETTE0 0x122
#define GEN6_FORMAT_P8A8_UNORM_PALETTE1 0x123
#define GEN6_FORMAT_A1B5G5R5_UNORM 0x124
#define GEN6_FORMAT_A4B4G4R4_UNORM 0x125
#define GEN6_FORMAT_L8A8_UINT 0x126
#define GEN6_FORMAT_L8A8_SINT 0x127
#define GEN6_FORMAT_R8_UNORM 0x140
#define GEN6_FORMAT_R8_SNORM 0x141
#define GEN6_FORMAT_R8_SINT 0x142
#define GEN6_FORMAT_R8_UINT 0x143
#define GEN6_FORMAT_A8_UNORM 0x144
#define GEN6_FORMAT_I8_UNORM 0x145
#define GEN6_FORMAT_L8_UNORM 0x146
#define GEN6_FORMAT_P4A4_UNORM_PALETTE0 0x147
#define GEN6_FORMAT_A4P4_UNORM_PALETTE0 0x148
#define GEN6_FORMAT_R8_SSCALED 0x149
#define GEN6_FORMAT_R8_USCALED 0x14a
#define GEN6_FORMAT_P8_UNORM_PALETTE0 0x14b
#define GEN6_FORMAT_L8_UNORM_SRGB 0x14c
#define GEN6_FORMAT_P8_UNORM_PALETTE1 0x14d
#define GEN6_FORMAT_P4A4_UNORM_PALETTE1 0x14e
#define GEN6_FORMAT_A4P4_UNORM_PALETTE1 0x14f
#define GEN6_FORMAT_Y8_UNORM 0x150
#define GEN6_FORMAT_L8_UINT 0x152
#define GEN6_FORMAT_L8_SINT 0x153
#define GEN6_FORMAT_I8_UINT 0x154
#define GEN6_FORMAT_I8_SINT 0x155
#define GEN6_FORMAT_DXT1_RGB_SRGB 0x180
#define GEN6_FORMAT_R1_UNORM 0x181
#define GEN6_FORMAT_YCRCB_NORMAL 0x182
#define GEN6_FORMAT_YCRCB_SWAPUVY 0x183
#define GEN6_FORMAT_P2_UNORM_PALETTE0 0x184
#define GEN6_FORMAT_P2_UNORM_PALETTE1 0x185
#define GEN6_FORMAT_BC1_UNORM 0x186
#define GEN6_FORMAT_BC2_UNORM 0x187
#define GEN6_FORMAT_BC3_UNORM 0x188
#define GEN6_FORMAT_BC4_UNORM 0x189
#define GEN6_FORMAT_BC5_UNORM 0x18a
#define GEN6_FORMAT_BC1_UNORM_SRGB 0x18b
#define GEN6_FORMAT_BC2_UNORM_SRGB 0x18c
#define GEN6_FORMAT_BC3_UNORM_SRGB 0x18d
#define GEN6_FORMAT_MONO8 0x18e
#define GEN6_FORMAT_YCRCB_SWAPUV 0x18f
#define GEN6_FORMAT_YCRCB_SWAPY 0x190
#define GEN6_FORMAT_DXT1_RGB 0x191
#define GEN6_FORMAT_FXT1 0x192
#define GEN6_FORMAT_R8G8B8_UNORM 0x193
#define GEN6_FORMAT_R8G8B8_SNORM 0x194
#define GEN6_FORMAT_R8G8B8_SSCALED 0x195
#define GEN6_FORMAT_R8G8B8_USCALED 0x196
#define GEN6_FORMAT_R64G64B64A64_FLOAT 0x197
#define GEN6_FORMAT_R64G64B64_FLOAT 0x198
#define GEN6_FORMAT_BC4_SNORM 0x199
#define GEN6_FORMAT_BC5_SNORM 0x19a
#define GEN6_FORMAT_R16G16B16_FLOAT 0x19b
#define GEN6_FORMAT_R16G16B16_UNORM 0x19c
#define GEN6_FORMAT_R16G16B16_SNORM 0x19d
#define GEN6_FORMAT_R16G16B16_SSCALED 0x19e
#define GEN6_FORMAT_R16G16B16_USCALED 0x19f
#define GEN6_FORMAT_BC6H_SF16 0x1a1
#define GEN6_FORMAT_BC7_UNORM 0x1a2
#define GEN6_FORMAT_BC7_UNORM_SRGB 0x1a3
#define GEN6_FORMAT_BC6H_UF16 0x1a4
#define GEN6_FORMAT_PLANAR_420_8 0x1a5
#define GEN6_FORMAT_R8G8B8_UNORM_SRGB 0x1a8
#define GEN6_FORMAT_ETC1_RGB8 0x1a9
#define GEN6_FORMAT_ETC2_RGB8 0x1aa
#define GEN6_FORMAT_EAC_R11 0x1ab
#define GEN6_FORMAT_EAC_RG11 0x1ac
#define GEN6_FORMAT_EAC_SIGNED_R11 0x1ad
#define GEN6_FORMAT_EAC_SIGNED_RG11 0x1ae
#define GEN6_FORMAT_ETC2_SRGB8 0x1af
#define GEN6_FORMAT_R16G16B16_UINT 0x1b0
#define GEN6_FORMAT_R16G16B16_SINT 0x1b1
#define GEN6_FORMAT_R32_SFIXED 0x1b2
#define GEN6_FORMAT_R10G10B10A2_SNORM 0x1b3
#define GEN6_FORMAT_R10G10B10A2_USCALED 0x1b4
#define GEN6_FORMAT_R10G10B10A2_SSCALED 0x1b5
#define GEN6_FORMAT_R10G10B10A2_SINT 0x1b6
#define GEN6_FORMAT_B10G10R10A2_SNORM 0x1b7
#define GEN6_FORMAT_B10G10R10A2_USCALED 0x1b8
#define GEN6_FORMAT_B10G10R10A2_SSCALED 0x1b9
#define GEN6_FORMAT_B10G10R10A2_UINT 0x1ba
#define GEN6_FORMAT_B10G10R10A2_SINT 0x1bb
#define GEN6_FORMAT_R64G64B64A64_PASSTHRU 0x1bc
#define GEN6_FORMAT_R64G64B64_PASSTHRU 0x1bd
#define GEN6_FORMAT_ETC2_RGB8_PTA 0x1c0
#define GEN6_FORMAT_ETC2_SRGB8_PTA 0x1c1
#define GEN6_FORMAT_ETC2_EAC_RGBA8 0x1c2
#define GEN6_FORMAT_ETC2_EAC_SRGB8_A8 0x1c3
#define GEN6_FORMAT_R8G8B8_UINT 0x1c8
#define GEN6_FORMAT_R8G8B8_SINT 0x1c9
#define GEN6_FORMAT_RAW 0x1ff
#define GEN6_SURFTYPE_1D 0x0
#define GEN6_SURFTYPE_2D 0x1
#define GEN6_SURFTYPE_3D 0x2
#define GEN6_SURFTYPE_CUBE 0x3
#define GEN6_SURFTYPE_BUFFER 0x4
#define GEN7_SURFTYPE_STRBUF 0x5
#define GEN6_SURFTYPE_NULL 0x7
#define GEN6_TILING_NONE 0x0
#define GEN6_TILING_X 0x2
#define GEN6_TILING_Y 0x3
#define GEN7_CLEAR_COLOR_ZERO 0x0
#define GEN7_CLEAR_COLOR_ONE 0x1
#define GEN75_SCS_ZERO 0x0
#define GEN75_SCS_ONE 0x1
#define GEN75_SCS_RED 0x4
#define GEN75_SCS_GREEN 0x5
#define GEN75_SCS_BLUE 0x6
#define GEN75_SCS_ALPHA 0x7
#define GEN6_MOCS_LLC__MASK 0x00000003
#define GEN6_MOCS_LLC__SHIFT 0
#define GEN6_MOCS_LLC_PTE 0x0
#define GEN6_MOCS_LLC_UC 0x1
#define GEN6_MOCS_LLC_ON 0x2
#define GEN7_MOCS_LLC__MASK 0x00000002
#define GEN7_MOCS_LLC__SHIFT 1
#define GEN7_MOCS_LLC_PTE (0x0 << 1)
#define GEN7_MOCS_LLC_ON (0x1 << 1)
#define GEN75_MOCS_LLC__MASK 0x00000006
#define GEN75_MOCS_LLC__SHIFT 1
#define GEN75_MOCS_LLC_PTE (0x0 << 1)
#define GEN75_MOCS_LLC_UC (0x1 << 1)
#define GEN75_MOCS_LLC_ON (0x2 << 1)
#define GEN75_MOCS_LLC_ELLC (0x3 << 1)
#define GEN7_MOCS_L3__MASK 0x00000001
#define GEN7_MOCS_L3__SHIFT 0
#define GEN7_MOCS_L3_UC 0x0
#define GEN7_MOCS_L3_ON 0x1
#define GEN6_SURFACE_STATE__SIZE 8
#define GEN6_SURFACE_DW0_TYPE__MASK 0xe0000000
#define GEN6_SURFACE_DW0_TYPE__SHIFT 29
#define GEN6_SURFACE_DW0_FORMAT__MASK 0x07fc0000
#define GEN6_SURFACE_DW0_FORMAT__SHIFT 18
#define GEN6_SURFACE_DW0_VSTRIDE (0x1 << 12)
#define GEN6_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11)
#define GEN6_SURFACE_DW0_MIPLAYOUT__MASK 0x00000400
#define GEN6_SURFACE_DW0_MIPLAYOUT__SHIFT 10
#define GEN6_SURFACE_DW0_MIPLAYOUT_BELOW (0x0 << 10)
#define GEN6_SURFACE_DW0_MIPLAYOUT_RIGHT (0x1 << 10)
#define GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE (0x1 << 9)
#define GEN6_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8)
#define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0
#define GEN6_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6
#define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f
#define GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0
#define GEN6_SURFACE_DW2_HEIGHT__MASK 0xfff80000
#define GEN6_SURFACE_DW2_HEIGHT__SHIFT 19
#define GEN6_SURFACE_DW2_WIDTH__MASK 0x0007ffc0
#define GEN6_SURFACE_DW2_WIDTH__SHIFT 6
#define GEN6_SURFACE_DW2_MIP_COUNT_LOD__MASK 0x0000003c
#define GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT 2
#define GEN6_SURFACE_DW2_RTROTATE__MASK 0x00000003
#define GEN6_SURFACE_DW2_RTROTATE__SHIFT 0
#define GEN6_SURFACE_DW2_RTROTATE_0DEG 0x0
#define GEN6_SURFACE_DW2_RTROTATE_90DEG 0x1
#define GEN6_SURFACE_DW2_RTROTATE_270DEG 0x3
#define GEN6_SURFACE_DW3_DEPTH__MASK 0xffe00000
#define GEN6_SURFACE_DW3_DEPTH__SHIFT 21
#define GEN6_SURFACE_DW3_PITCH__MASK 0x000ffff8
#define GEN6_SURFACE_DW3_PITCH__SHIFT 3
#define GEN6_SURFACE_DW3_TILING__MASK 0x00000003
#define GEN6_SURFACE_DW3_TILING__SHIFT 0
#define GEN6_SURFACE_DW4_MIN_LOD__MASK 0xf0000000
#define GEN6_SURFACE_DW4_MIN_LOD__SHIFT 28
#define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x0ffe0000
#define GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 17
#define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0001ff00
#define GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 8
#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000070
#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 4
#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 4)
#define GEN6_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 4)
#define GEN6_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007
#define GEN6_SURFACE_DW4_MSPOS_INDEX__SHIFT 0
#define GEN6_SURFACE_DW5_X_OFFSET__MASK 0xfe000000
#define GEN6_SURFACE_DW5_X_OFFSET__SHIFT 25
#define GEN6_SURFACE_DW5_VALIGN__MASK 0x01000000
#define GEN6_SURFACE_DW5_VALIGN__SHIFT 24
#define GEN6_SURFACE_DW5_VALIGN_2 (0x0 << 24)
#define GEN6_SURFACE_DW5_VALIGN_4 (0x1 << 24)
#define GEN6_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000
#define GEN6_SURFACE_DW5_Y_OFFSET__SHIFT 20
#define GEN6_SURFACE_DW5_MOCS__MASK 0x000f0000
#define GEN6_SURFACE_DW5_MOCS__SHIFT 16
#define GEN7_SURFACE_DW0_TYPE__MASK 0xe0000000
#define GEN7_SURFACE_DW0_TYPE__SHIFT 29
#define GEN7_SURFACE_DW0_IS_ARRAY (0x1 << 28)
#define GEN7_SURFACE_DW0_FORMAT__MASK 0x07fc0000
#define GEN7_SURFACE_DW0_FORMAT__SHIFT 18
#define GEN7_SURFACE_DW0_VALIGN__MASK 0x00030000
#define GEN7_SURFACE_DW0_VALIGN__SHIFT 16
#define GEN7_SURFACE_DW0_VALIGN_2 (0x0 << 16)
#define GEN7_SURFACE_DW0_VALIGN_4 (0x1 << 16)
#define GEN7_SURFACE_DW0_HALIGN__MASK 0x00008000
#define GEN7_SURFACE_DW0_HALIGN__SHIFT 15
#define GEN7_SURFACE_DW0_HALIGN_4 (0x0 << 15)
#define GEN7_SURFACE_DW0_HALIGN_8 (0x1 << 15)
#define GEN7_SURFACE_DW0_TILING__MASK 0x00006000
#define GEN7_SURFACE_DW0_TILING__SHIFT 13
#define GEN7_SURFACE_DW0_VSTRIDE (0x1 << 12)
#define GEN7_SURFACE_DW0_VSTRIDE_OFFSET (0x1 << 11)
#define GEN7_SURFACE_DW0_ARYSPC__MASK 0x00000400
#define GEN7_SURFACE_DW0_ARYSPC__SHIFT 10
#define GEN7_SURFACE_DW0_ARYSPC_FULL (0x0 << 10)
#define GEN7_SURFACE_DW0_ARYSPC_LOD0 (0x1 << 10)
#define GEN7_SURFACE_DW0_RENDER_CACHE_RW (0x1 << 8)
#define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__MASK 0x000000c0
#define GEN7_SURFACE_DW0_MEDIA_BOUNDARY_PIXEL_MODE__SHIFT 6
#define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK 0x0000003f
#define GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__SHIFT 0
#define GEN7_SURFACE_DW2_HEIGHT__MASK 0x3fff0000
#define GEN7_SURFACE_DW2_HEIGHT__SHIFT 16
#define GEN7_SURFACE_DW2_WIDTH__MASK 0x00003fff
#define GEN7_SURFACE_DW2_WIDTH__SHIFT 0
#define GEN7_SURFACE_DW3_DEPTH__MASK 0xffe00000
#define GEN7_SURFACE_DW3_DEPTH__SHIFT 21
#define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__MASK 0x001c0000
#define GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT 18
#define GEN7_SURFACE_DW3_PITCH__MASK 0x0003ffff
#define GEN7_SURFACE_DW3_PITCH__SHIFT 0
#define GEN7_SURFACE_DW4_RTROTATE__MASK 0x60000000
#define GEN7_SURFACE_DW4_RTROTATE__SHIFT 29
#define GEN7_SURFACE_DW4_RTROTATE_0DEG (0x0 << 29)
#define GEN7_SURFACE_DW4_RTROTATE_90DEG (0x1 << 29)
#define GEN7_SURFACE_DW4_RTROTATE_270DEG (0x3 << 29)
#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__MASK 0x1ffc0000
#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT 18
#define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__MASK 0x0003ff80
#define GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT 7
#define GEN7_SURFACE_DW4_MSFMT__MASK 0x00000040
#define GEN7_SURFACE_DW4_MSFMT__SHIFT 6
#define GEN7_SURFACE_DW4_MSFMT_MSS (0x0 << 6)
#define GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL (0x1 << 6)
#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__MASK 0x00000038
#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT 3
#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1 (0x0 << 3)
#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4 (0x2 << 3)
#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8 (0x3 << 3)
#define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007
#define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT 0
#define GEN7_SURFACE_DW5_X_OFFSET__MASK 0xfe000000
#define GEN7_SURFACE_DW5_X_OFFSET__SHIFT 25
#define GEN7_SURFACE_DW5_Y_OFFSET__MASK 0x00f00000
#define GEN7_SURFACE_DW5_Y_OFFSET__SHIFT 20
#define GEN7_SURFACE_DW5_MOCS__MASK 0x000f0000
#define GEN7_SURFACE_DW5_MOCS__SHIFT 16
#define GEN7_SURFACE_DW5_MIN_LOD__MASK 0x000000f0
#define GEN7_SURFACE_DW5_MIN_LOD__SHIFT 4
#define GEN7_SURFACE_DW5_MIP_COUNT_LOD__MASK 0x0000000f
#define GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT 0
#define GEN7_SURFACE_DW6_UV_X_OFFSET__MASK 0x3fff0000
#define GEN7_SURFACE_DW6_UV_X_OFFSET__SHIFT 16
#define GEN7_SURFACE_DW6_UV_Y_OFFSET__MASK 0x00003fff
#define GEN7_SURFACE_DW6_UV_Y_OFFSET__SHIFT 0
#define GEN7_SURFACE_DW6_MCS_ADDR__MASK 0xfffff000
#define GEN7_SURFACE_DW6_MCS_ADDR__SHIFT 12
#define GEN7_SURFACE_DW6_MCS_ADDR__SHR 12
#define GEN7_SURFACE_DW6_MCS_PITCH__MASK 0x00000ff8
#define GEN7_SURFACE_DW6_MCS_PITCH__SHIFT 3
#define GEN7_SURFACE_DW6_MCS_ENABLE (0x1 << 0)
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ENABLE (0x1 << 1)
#define GEN7_SURFACE_DW7_CC_R__MASK 0x80000000
#define GEN7_SURFACE_DW7_CC_R__SHIFT 31
#define GEN7_SURFACE_DW7_CC_G__MASK 0x40000000
#define GEN7_SURFACE_DW7_CC_G__SHIFT 30
#define GEN7_SURFACE_DW7_CC_B__MASK 0x20000000
#define GEN7_SURFACE_DW7_CC_B__SHIFT 29
#define GEN7_SURFACE_DW7_CC_A__MASK 0x10000000
#define GEN7_SURFACE_DW7_CC_A__SHIFT 28
#define GEN75_SURFACE_DW7_SCS_R__MASK 0x0e000000
#define GEN75_SURFACE_DW7_SCS_R__SHIFT 25
#define GEN75_SURFACE_DW7_SCS_G__MASK 0x01c00000
#define GEN75_SURFACE_DW7_SCS_G__SHIFT 22
#define GEN75_SURFACE_DW7_SCS_B__MASK 0x00380000
#define GEN75_SURFACE_DW7_SCS_B__SHIFT 19
#define GEN75_SURFACE_DW7_SCS_A__MASK 0x00070000
#define GEN75_SURFACE_DW7_SCS_A__SHIFT 16
#define GEN7_SURFACE_DW7_RES_MIN_LOD__MASK 0x00000fff
#define GEN7_SURFACE_DW7_RES_MIN_LOD__SHIFT 0
#define GEN6_BINDING_TABLE_STATE__SIZE 256
#define GEN6_BINDING_TABLE_SURFACE_ADDR__MASK 0xffffffe0
#define GEN6_BINDING_TABLE_SURFACE_ADDR__SHIFT 5
#define GEN6_BINDING_TABLE_SURFACE_ADDR__SHR 5
#endif /* GEN_RENDER_SURFACE_XML */

200
src/gallium/drivers/ilo/genhw/genhw.h Normal file
View File

@ -0,0 +1,200 @@
/*
* Mesa 3-D graphics library
*
* Copyright (C) 2014 LunarG, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GENHW_H
#define GENHW_H
#include "pipe/p_compiler.h"
#include "util/u_debug.h"
#include "intel_reg.h"
#include "brw_defines.h"
#include "gen_regs.xml.h"
#include "gen_mi.xml.h"
#include "gen_blitter.xml.h"
#include "gen_render_surface.xml.h"
#include "gen_render_dynamic.xml.h"
#include "gen_render_3d.xml.h"
#include "gen_eu_isa.xml.h"
#include "gen_eu_message.xml.h"
#define GEN_MI_CMD(op) (GEN6_MI_TYPE_MI | GEN6_MI_OPCODE_ ## op)
#define GEN_BLITTER_CMD(op) \
(GEN6_BLITTER_TYPE_BLITTER | GEN6_BLITTER_OPCODE_ ## op)
#define GEN_RENDER_CMD(subtype, op) \
(GEN6_RENDER_TYPE_RENDER | \
GEN6_RENDER_SUBTYPE_ ## subtype | \
GEN6_RENDER_OPCODE_ ## op)
static inline bool
gen_is_snb(int devid)
{
return (devid == 0x0102 || /* GT1 desktop */
devid == 0x0112 || /* GT2 desktop */
devid == 0x0122 || /* GT2_PLUS desktop */
devid == 0x0106 || /* GT1 mobile */
devid == 0x0116 || /* GT2 mobile */
devid == 0x0126 || /* GT2_PLUS mobile */
devid == 0x010a); /* GT1 server */
}
static inline int
gen_get_snb_gt(int devid)
{
assert(gen_is_snb(devid));
return (devid & 0x30) ? 2 : 1;
}
static inline bool
gen_is_ivb(int devid)
{
return (devid == 0x0152 || /* GT1 desktop */
devid == 0x0162 || /* GT2 desktop */
devid == 0x0156 || /* GT1 mobile */
devid == 0x0166 || /* GT2 mobile */
devid == 0x015a || /* GT1 server */
devid == 0x016a); /* GT2 server */
}
static inline int
gen_get_ivb_gt(int devid)
{
assert(gen_is_ivb(devid));
return (devid & 0x30) >> 4;
}
static inline bool
gen_is_hsw(int devid)
{
return (devid == 0x0402 || /* GT1 desktop */
devid == 0x0412 || /* GT2 desktop */
devid == 0x0422 || /* GT3 desktop */
devid == 0x0406 || /* GT1 mobile */
devid == 0x0416 || /* GT2 mobile */
devid == 0x0426 || /* GT2 mobile */
devid == 0x040a || /* GT1 server */
devid == 0x041a || /* GT2 server */
devid == 0x042a || /* GT3 server */
devid == 0x040b || /* GT1 reserved */
devid == 0x041b || /* GT2 reserved */
devid == 0x042b || /* GT3 reserved */
devid == 0x040e || /* GT1 reserved */
devid == 0x041e || /* GT2 reserved */
devid == 0x042e || /* GT3 reserved */
devid == 0x0c02 || /* SDV */
devid == 0x0c12 ||
devid == 0x0c22 ||
devid == 0x0c06 ||
devid == 0x0c16 ||
devid == 0x0c26 ||
devid == 0x0c0a ||
devid == 0x0c1a ||
devid == 0x0c2a ||
devid == 0x0c0b ||
devid == 0x0c1b ||
devid == 0x0c2b ||
devid == 0x0c0e ||
devid == 0x0c1e ||
devid == 0x0c2e ||
devid == 0x0a02 || /* ULT */
devid == 0x0a12 ||
devid == 0x0a22 ||
devid == 0x0a06 ||
devid == 0x0a16 ||
devid == 0x0a26 ||
devid == 0x0a0a ||
devid == 0x0a1a ||
devid == 0x0a2a ||
devid == 0x0a0b ||
devid == 0x0a1b ||
devid == 0x0a2b ||
devid == 0x0a0e ||
devid == 0x0a1e ||
devid == 0x0a2e ||
devid == 0x0d02 || /* CRW */
devid == 0x0d12 ||
devid == 0x0d22 ||
devid == 0x0d06 ||
devid == 0x0d16 ||
devid == 0x0d26 ||
devid == 0x0d0a ||
devid == 0x0d1a ||
devid == 0x0d2a ||
devid == 0x0d0b ||
devid == 0x0d1b ||
devid == 0x0d2b ||
devid == 0x0d0e ||
devid == 0x0d1e ||
devid == 0x0d2e);
}
static inline int
gen_get_hsw_gt(int devid)
{
assert(gen_is_hsw(devid));
return ((devid & 0x30) >> 4) + 1;
}
static inline bool
gen_is_vlv(int devid)
{
return (devid == 0x0f30 ||
devid == 0x0f31 ||
devid == 0x0f32 ||
devid == 0x0f33 ||
devid == 0x0157 ||
devid == 0x0155);
}
static inline bool
gen_is_atom(int devid)
{
return gen_is_vlv(devid);
}
static inline bool
gen_is_desktop(int devid)
{
assert(!gen_is_atom(devid));
return ((devid & 0xf) == 0x2);
}
static inline bool
gen_is_mobile(int devid)
{
assert(!gen_is_atom(devid));
return ((devid & 0xf) == 0x6);
}
static inline bool
gen_is_server(int devid)
{
assert(!gen_is_atom(devid));
return ((devid & 0xf) == 0xa);
}
#endif /* GENHW_H */

2
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
View File

@ -25,9 +25,9 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "util/u_dual_blend.h"
#include "util/u_prim.h"
#include "intel_reg.h"
#include "ilo_blitter.h"
#include "ilo_3d.h"

2
src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
View File

@ -25,8 +25,8 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "util/u_dual_blend.h"
#include "intel_reg.h"
#include "ilo_blitter.h"
#include "ilo_context.h"

2
src/gallium/drivers/ilo/ilo_blitter_blt.c
View File

@ -25,8 +25,8 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "util/u_pack_color.h"
#include "intel_reg.h"
#include "ilo_3d.h"
#include "ilo_context.h"

1
src/gallium/drivers/ilo/ilo_context.c
View File

@ -26,7 +26,6 @@
*/
#include "util/u_upload_mgr.h"
#include "intel_chipset.h"
#include "ilo_3d.h"
#include "ilo_blit.h"

2
src/gallium/drivers/ilo/ilo_cp.c
View File

@ -25,7 +25,7 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "intel_reg.h" /* for MI_xxx */
#include "genhw/genhw.h" /* for MI_xxx */
#include "intel_winsys.h"
#include "ilo_cp.h"

2
src/gallium/drivers/ilo/ilo_format.c
View File

@ -25,8 +25,8 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "vl/vl_video_buffer.h"
#include "brw_defines.h"
#include "ilo_screen.h"
#include "ilo_format.h"

2
src/gallium/drivers/ilo/ilo_format.h
View File

@ -28,7 +28,7 @@
#ifndef ILO_FORMAT_H
#define ILO_FORMAT_H
#include "brw_defines.h"
#include "genhw/genhw.h"
#include "ilo_common.h"

3
src/gallium/drivers/ilo/ilo_gpe_gen6.c
View File

@ -25,11 +25,10 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "util/u_dual_blend.h"
#include "util/u_framebuffer.h"
#include "util/u_half.h"
#include "brw_defines.h"
#include "intel_reg.h"
#include "ilo_context.h"
#include "ilo_format.h"

3
src/gallium/drivers/ilo/ilo_gpe_gen6.h
View File

@ -28,8 +28,7 @@
#ifndef ILO_GPE_GEN6_H
#define ILO_GPE_GEN6_H
#include "brw_defines.h"
#include "intel_reg.h"
#include "genhw/genhw.h"
#include "intel_winsys.h"
#include "ilo_common.h"

3
src/gallium/drivers/ilo/ilo_gpe_gen7.c
View File

@ -25,9 +25,8 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h"
#include "util/u_resource.h"
#include "brw_defines.h"
#include "intel_reg.h"
#include "ilo_format.h"
#include "ilo_resource.h"

155
src/gallium/drivers/ilo/ilo_screen.c
View File

@ -28,8 +28,7 @@
#include "util/u_format_s3tc.h"
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
#include "intel_chipset.h"
#include "intel_reg.h" /* for TIMESTAMP */
#include "genhw/genhw.h" /* for TIMESTAMP */
#include "intel_winsys.h"
#include "ilo_context.h"
@ -457,88 +456,38 @@ static const char *
ilo_get_name(struct pipe_screen *screen)
{
struct ilo_screen *is = ilo_screen(screen);
const char *chipset;
const char *chipset = NULL;
/* stolen from classic i965 */
switch (is->dev.devid) {
case PCI_CHIP_SANDYBRIDGE_GT1:
case PCI_CHIP_SANDYBRIDGE_GT2:
case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
chipset = "Intel(R) Sandybridge Desktop";
break;
case PCI_CHIP_SANDYBRIDGE_M_GT1:
case PCI_CHIP_SANDYBRIDGE_M_GT2:
case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
chipset = "Intel(R) Sandybridge Mobile";
break;
case PCI_CHIP_SANDYBRIDGE_S:
chipset = "Intel(R) Sandybridge Server";
break;
case PCI_CHIP_IVYBRIDGE_GT1:
case PCI_CHIP_IVYBRIDGE_GT2:
chipset = "Intel(R) Ivybridge Desktop";
break;
case PCI_CHIP_IVYBRIDGE_M_GT1:
case PCI_CHIP_IVYBRIDGE_M_GT2:
chipset = "Intel(R) Ivybridge Mobile";
break;
case PCI_CHIP_IVYBRIDGE_S_GT1:
case PCI_CHIP_IVYBRIDGE_S_GT2:
chipset = "Intel(R) Ivybridge Server";
break;
case PCI_CHIP_BAYTRAIL_M_1:
case PCI_CHIP_BAYTRAIL_M_2:
case PCI_CHIP_BAYTRAIL_M_3:
case PCI_CHIP_BAYTRAIL_M_4:
case PCI_CHIP_BAYTRAIL_D:
if (gen_is_vlv(is->dev.devid)) {
chipset = "Intel(R) Bay Trail";
break;
case PCI_CHIP_HASWELL_GT1:
case PCI_CHIP_HASWELL_GT2:
case PCI_CHIP_HASWELL_GT3:
case PCI_CHIP_HASWELL_SDV_GT1:
case PCI_CHIP_HASWELL_SDV_GT2:
case PCI_CHIP_HASWELL_SDV_GT3:
case PCI_CHIP_HASWELL_ULT_GT1:
case PCI_CHIP_HASWELL_ULT_GT2:
case PCI_CHIP_HASWELL_ULT_GT3:
case PCI_CHIP_HASWELL_CRW_GT1:
case PCI_CHIP_HASWELL_CRW_GT2:
case PCI_CHIP_HASWELL_CRW_GT3:
chipset = "Intel(R) Haswell Desktop";
break;
case PCI_CHIP_HASWELL_M_GT1:
case PCI_CHIP_HASWELL_M_GT2:
case PCI_CHIP_HASWELL_M_GT3:
case PCI_CHIP_HASWELL_SDV_M_GT1:
case PCI_CHIP_HASWELL_SDV_M_GT2:
case PCI_CHIP_HASWELL_SDV_M_GT3:
case PCI_CHIP_HASWELL_ULT_M_GT1:
case PCI_CHIP_HASWELL_ULT_M_GT2:
case PCI_CHIP_HASWELL_ULT_M_GT3:
case PCI_CHIP_HASWELL_CRW_M_GT1:
case PCI_CHIP_HASWELL_CRW_M_GT2:
case PCI_CHIP_HASWELL_CRW_M_GT3:
chipset = "Intel(R) Haswell Mobile";
break;
case PCI_CHIP_HASWELL_S_GT1:
case PCI_CHIP_HASWELL_S_GT2:
case PCI_CHIP_HASWELL_S_GT3:
case PCI_CHIP_HASWELL_SDV_S_GT1:
case PCI_CHIP_HASWELL_SDV_S_GT2:
case PCI_CHIP_HASWELL_SDV_S_GT3:
case PCI_CHIP_HASWELL_ULT_S_GT1:
case PCI_CHIP_HASWELL_ULT_S_GT2:
case PCI_CHIP_HASWELL_ULT_S_GT3:
case PCI_CHIP_HASWELL_CRW_S_GT1:
case PCI_CHIP_HASWELL_CRW_S_GT2:
case PCI_CHIP_HASWELL_CRW_S_GT3:
chipset = "Intel(R) Haswell Server";
break;
default:
chipset = "Unknown Intel Chipset";
break;
}
else if (gen_is_hsw(is->dev.devid)) {
if (gen_is_desktop(is->dev.devid))
chipset = "Intel(R) Haswell Desktop";
else if (gen_is_mobile(is->dev.devid))
chipset = "Intel(R) Haswell Mobile";
else if (gen_is_server(is->dev.devid))
chipset = "Intel(R) Haswell Server";
}
else if (gen_is_ivb(is->dev.devid)) {
if (gen_is_desktop(is->dev.devid))
chipset = "Intel(R) Ivybridge Desktop";
else if (gen_is_mobile(is->dev.devid))
chipset = "Intel(R) Ivybridge Mobile";
else if (gen_is_server(is->dev.devid))
chipset = "Intel(R) Ivybridge Server";
}
else if (gen_is_snb(is->dev.devid)) {
if (gen_is_desktop(is->dev.devid))
chipset = "Intel(R) Sandybridge Desktop";
else if (gen_is_mobile(is->dev.devid))
chipset = "Intel(R) Sandybridge Mobile";
else if (gen_is_server(is->dev.devid))
chipset = "Intel(R) Sandybridge Server";
}
if (!chipset)
chipset = "Unknown Intel Chipset";
return chipset;
}
@ -698,45 +647,21 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
* 256k 8096 4096"
*/
if (IS_HASWELL(info->devid)) {
if (gen_is_hsw(info->devid)) {
dev->gen = ILO_GEN(7.5);
if (IS_HSW_GT3(info->devid)) {
dev->gt = 3;
dev->urb_size = 512 * 1024;
}
else if (IS_HSW_GT2(info->devid)) {
dev->gt = 2;
dev->urb_size = 256 * 1024;
}
else {
dev->gt = 1;
dev->urb_size = 128 * 1024;
}
dev->gt = gen_get_hsw_gt(info->devid);
dev->urb_size = ((dev->gt == 3) ? 512 :
(dev->gt == 2) ? 256 : 128) * 1024;
}
else if (IS_GEN7(info->devid)) {
else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
dev->gen = ILO_GEN(7);
if (IS_IVB_GT2(info->devid)) {
dev->gt = 2;
dev->urb_size = 256 * 1024;
}
else {
dev->gt = 1;
dev->urb_size = 128 * 1024;
}
dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
dev->urb_size = ((dev->gt == 2) ? 256 : 128) * 1024;
}
else if (IS_GEN6(info->devid)) {
else if (gen_is_snb(info->devid)) {
dev->gen = ILO_GEN(6);
if (IS_SNB_GT2(info->devid)) {
dev->gt = 2;
dev->urb_size = 64 * 1024;
}
else {
dev->gt = 1;
dev->urb_size = 32 * 1024;
}
dev->gt = gen_get_snb_gt(info->devid);
dev->urb_size = ((dev->gt == 2) ? 64 : 32) * 1024;
}
else {
ilo_err("unknown GPU generation\n");

2
src/gallium/drivers/ilo/ilo_shader.c
View File

@ -25,9 +25,9 @@
* Chia-I Wu <olv@lunarg.com>
*/
#include "genhw/genhw.h" /* for SBE setup */
#include "tgsi/tgsi_parse.h"
#include "intel_winsys.h"
#include "brw_defines.h" /* for SBE setup */
#include "shader/ilo_shader_internal.h"
#include "ilo_state.h"

2
src/gallium/drivers/ilo/shader/toy_compiler.h
View File

@ -28,8 +28,8 @@
#ifndef TOY_COMPILER_H
#define TOY_COMPILER_H
#include "genhw/genhw.h"
#include "util/u_slab.h"
#include "brw_defines.h"
#include "ilo_common.h"
#include "toy_compiler_reg.h"