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radv: fix stencil regression since new addrlib import 

The addrlib import meant we'd return after we attempted
to setup the no stencil bits for an S8_UINT, now we break
and use the stencil level info when creating stencil DB
info.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-04-13 14:36:26 +10:00
parent 4bcebe10ca
commit 01d0c5a922
2 changed files with 9 additions and 1 deletions
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8
src/amd/vulkan/radv_device.c
View File

@ -2732,6 +2732,7 @@ radv_initialise_ds_surface(struct radv_device *device,
unsigned format;
uint64_t va, s_offs, z_offs;
const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
bool stencil_only = false;
memset(ds, 0, sizeof(*ds));
switch (iview->vk_format) {
case VK_FORMAT_D24_UNORM_S8_UINT:
@ -2750,6 +2751,10 @@ radv_initialise_ds_surface(struct radv_device *device,
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
ds->offset_scale = 1.0f;
break;
case VK_FORMAT_S8_UINT:
stencil_only = true;
level_info = &iview->image->surface.stencil_level[level];
break;
default:
break;
}
@ -2784,6 +2789,9 @@ radv_initialise_ds_surface(struct radv_device *device,
unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
if (stencil_only)
tile_mode = stencil_tile_mode;
ds->db_depth_info |=
S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |

2
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
View File

@ -486,7 +486,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
r = radv_compute_level(ws->addrlib, surf, false, level, type, compressed,
&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
if (r)
return r;
break;
if (level == 0) {
surf->bo_alignment = AddrSurfInfoOut.baseAlign;