turnip: Configure VPC for geometry shaders
This commit updates tu6_emit_vpc to selectively emit GS-specifc configuration. Most of this is repurposed from fd6_program.c. This also refactors `link_geometry_stages` to ir3_nir_lower_tess.c so it can be shared between fd and tu. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4436>
This commit is contained in:
parent
6eabd6bd51
commit
012773be26
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@ -60,4 +60,8 @@ bool ir3_nir_analyze_ubo_ranges(nir_shader *nir, struct ir3_shader *shader);
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nir_ssa_def *
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nir_ssa_def *
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ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift);
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ir3_nir_try_propagate_bit_shift(nir_builder *b, nir_ssa_def *offset, int32_t shift);
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uint32_t ir3_link_geometry_stages(const struct ir3_shader_variant *producer,
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const struct ir3_shader_variant *consumer,
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uint32_t *locs);
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#endif /* IR3_NIR_H_ */
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#endif /* IR3_NIR_H_ */
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@ -956,3 +956,39 @@ ir3_nir_lower_gs(nir_shader *shader, struct ir3_shader *s)
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nir_print_shader(shader, stderr);
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nir_print_shader(shader, stderr);
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}
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}
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}
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}
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uint32_t
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ir3_link_geometry_stages(const struct ir3_shader_variant *producer,
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const struct ir3_shader_variant *consumer,
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uint32_t *locs)
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{
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uint32_t num_loc = 0, factor;
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switch (consumer->type) {
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_GEOMETRY:
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/* These stages load with ldlw, which expects byte offsets. */
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factor = 4;
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break;
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case MESA_SHADER_TESS_EVAL:
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/* The tess eval shader uses ldg, which takes dword offsets. */
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factor = 1;
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break;
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default:
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unreachable("bad shader stage");
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}
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nir_foreach_variable(in_var, &consumer->shader->nir->inputs) {
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nir_foreach_variable(out_var, &producer->shader->nir->outputs) {
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if (in_var->data.location == out_var->data.location) {
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locs[in_var->data.driver_location] =
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producer->shader->output_loc[out_var->data.driver_location] * factor;
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debug_assert(num_loc <= in_var->data.driver_location + 1);
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num_loc = in_var->data.driver_location + 1;
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}
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}
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}
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return num_loc;
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}
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@ -27,6 +27,7 @@
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#include "tu_private.h"
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#include "tu_private.h"
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#include "ir3/ir3_nir.h"
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#include "main/menums.h"
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#include "main/menums.h"
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#include "nir/nir.h"
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#include "nir/nir.h"
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#include "nir/nir_builder.h"
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#include "nir/nir_builder.h"
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@ -686,18 +687,51 @@ tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base,
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tu_cs_emit_array(cs, dwords, size);
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tu_cs_emit_array(cs, dwords, size);
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}
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}
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static void
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tu6_emit_link_map(struct tu_cs *cs,
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const struct ir3_shader_variant *producer,
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const struct ir3_shader_variant *consumer) {
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const struct ir3_const_state *const_state = &consumer->shader->const_state;
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uint32_t base = const_state->offsets.primitive_map;
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uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
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num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
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int size = DIV_ROUND_UP(num_loc, 4);
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size = (MIN2(size + base, consumer->constlen) - base) * 4;
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tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
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patch_locs);
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}
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static uint16_t
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gl_primitive_to_tess(uint16_t primitive) {
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switch (primitive) {
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case GL_POINTS:
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return TESS_POINTS;
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case GL_LINE_STRIP:
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return TESS_LINES;
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case GL_TRIANGLE_STRIP:
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return TESS_CW_TRIS;
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default:
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unreachable("");
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}
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}
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static void
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static void
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tu6_emit_vpc(struct tu_cs *cs,
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tu6_emit_vpc(struct tu_cs *cs,
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const struct ir3_shader_variant *vs,
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const struct ir3_shader_variant *vs,
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const struct ir3_shader_variant *gs,
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const struct ir3_shader_variant *fs,
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const struct ir3_shader_variant *fs,
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bool binning_pass,
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bool binning_pass,
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struct tu_streamout_state *tf)
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struct tu_streamout_state *tf)
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{
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{
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bool has_gs = gs->type != MESA_SHADER_NONE;
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const struct ir3_shader_variant *last_shader = has_gs ? gs : vs;
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struct ir3_shader_linkage linkage = { 0 };
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struct ir3_shader_linkage linkage = { 0 };
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ir3_link_shaders(&linkage, vs, fs);
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ir3_link_shaders(&linkage, last_shader, fs);
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if (vs->shader->stream_output.num_outputs)
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if (last_shader->shader->stream_output.num_outputs)
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tu6_link_streamout(&linkage, vs);
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tu6_link_streamout(&linkage, last_shader);
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BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
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BITSET_DECLARE(vpc_var_enables, 128) = { 0 };
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for (uint32_t i = 0; i < linkage.cnt; i++) {
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for (uint32_t i = 0; i < linkage.cnt; i++) {
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@ -714,10 +748,17 @@ tu6_emit_vpc(struct tu_cs *cs,
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/* a6xx finds position/pointsize at the end */
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/* a6xx finds position/pointsize at the end */
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const uint32_t position_regid =
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const uint32_t position_regid =
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ir3_find_output_regid(vs, VARYING_SLOT_POS);
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ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
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const uint32_t pointsize_regid =
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const uint32_t pointsize_regid =
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ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
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ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
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uint32_t pointsize_loc = 0xff, position_loc = 0xff;
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const uint32_t layer_regid = has_gs ?
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ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
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uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
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if (layer_regid != regid(63, 0)) {
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layer_loc = linkage.max_loc;
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ir3_link_add(&linkage, layer_regid, 0x1, linkage.max_loc);
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}
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if (position_regid != regid(63, 0)) {
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if (position_regid != regid(63, 0)) {
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position_loc = linkage.max_loc;
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position_loc = linkage.max_loc;
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ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
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ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
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@ -727,30 +768,34 @@ tu6_emit_vpc(struct tu_cs *cs,
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ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
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ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
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}
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}
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if (vs->shader->stream_output.num_outputs)
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if (last_shader->shader->stream_output.num_outputs)
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tu6_setup_streamout(vs, &linkage, tf);
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tu6_setup_streamout(last_shader, &linkage, tf);
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/* map vs outputs to VPC */
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/* map outputs of the last shader to VPC */
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assert(linkage.cnt <= 32);
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assert(linkage.cnt <= 32);
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const uint32_t sp_vs_out_count = (linkage.cnt + 1) / 2;
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const uint32_t sp_out_count = DIV_ROUND_UP(linkage.cnt, 2);
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const uint32_t sp_vs_vpc_dst_count = (linkage.cnt + 3) / 4;
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const uint32_t sp_vpc_dst_count = DIV_ROUND_UP(linkage.cnt, 4);
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uint32_t sp_vs_out[16];
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uint32_t sp_out[16];
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uint32_t sp_vs_vpc_dst[8];
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uint32_t sp_vpc_dst[8];
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sp_vs_out[sp_vs_out_count - 1] = 0;
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sp_vs_vpc_dst[sp_vs_vpc_dst_count - 1] = 0;
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for (uint32_t i = 0; i < linkage.cnt; i++) {
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for (uint32_t i = 0; i < linkage.cnt; i++) {
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((uint16_t *) sp_vs_out)[i] =
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((uint16_t *) sp_out)[i] =
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A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
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A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
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A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
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A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
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((uint8_t *) sp_vs_vpc_dst)[i] =
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((uint8_t *) sp_vpc_dst)[i] =
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A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
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A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
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}
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}
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_vs_out_count);
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if (has_gs)
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tu_cs_emit_array(cs, sp_vs_out, sp_vs_out_count);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
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else
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
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tu_cs_emit_array(cs, sp_out, sp_out_count);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vs_vpc_dst_count);
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if (has_gs)
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tu_cs_emit_array(cs, sp_vs_vpc_dst, sp_vs_vpc_dst_count);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
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else
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
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tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
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tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
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tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
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@ -762,12 +807,84 @@ tu6_emit_vpc(struct tu_cs *cs,
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A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
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A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
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A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
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A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
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if (has_gs) {
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CTRL_REG0, 1);
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tu_cs_emit(cs, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
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A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
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A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
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COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
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tu6_emit_link_map(cs, vs, gs);
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uint32_t primitive_regid =
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ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
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tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
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A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
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A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
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tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
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tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
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tu_cs_emit(cs, CONDREG(layer_regid,
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A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
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uint32_t flags_regid = ir3_find_output_regid(gs,
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VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
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tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
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A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
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tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
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CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
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CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
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CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
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uint32_t vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
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uint16_t output =
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gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
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uint32_t invocations = gs->shader->nir->info.gs.invocations - 1;
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
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tu_cs_emit(cs,
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A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
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A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
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A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
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tu_cs_emit(cs, 0);
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tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
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tu_cs_emit(cs, 0);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
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tu_cs_emit(cs, 0xff);
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tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
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tu_cs_emit(cs, 0xffff00);
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/* Size of per-primitive alloction in ldlw memory in vec4s. */
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uint32_t vec4_size =
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gs->shader->nir->info.gs.vertices_in *
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DIV_ROUND_UP(vs->shader->output_size, 4);
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
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tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
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tu_cs_emit(cs, 0);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
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tu_cs_emit(cs, vs->shader->output_size);
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}
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
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tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
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tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
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tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
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tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
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tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
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(vs->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
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(last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
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}
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}
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static int
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static int
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||||||
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@ -1227,7 +1344,7 @@ tu6_emit_program(struct tu_cs *cs,
|
||||||
tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
|
tu6_emit_fs_config(cs, builder->shaders[MESA_SHADER_FRAGMENT], fs);
|
||||||
|
|
||||||
tu6_emit_vs_system_values(cs, vs);
|
tu6_emit_vs_system_values(cs, vs);
|
||||||
tu6_emit_vpc(cs, vs, fs, binning_pass, tf);
|
tu6_emit_vpc(cs, vs, gs, fs, binning_pass, tf);
|
||||||
tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
|
tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
|
||||||
tu6_emit_fs_inputs(cs, fs);
|
tu6_emit_fs_inputs(cs, fs);
|
||||||
tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
|
tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
|
||||||
|
|
|
@ -412,42 +412,6 @@ ir3_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t
|
|
||||||
link_geometry_stages(const struct ir3_shader_variant *producer,
|
|
||||||
const struct ir3_shader_variant *consumer,
|
|
||||||
uint32_t *locs)
|
|
||||||
{
|
|
||||||
uint32_t num_loc = 0, factor;
|
|
||||||
|
|
||||||
switch (consumer->type) {
|
|
||||||
case MESA_SHADER_TESS_CTRL:
|
|
||||||
case MESA_SHADER_GEOMETRY:
|
|
||||||
/* These stages load with ldlw, which expects byte offsets. */
|
|
||||||
factor = 4;
|
|
||||||
break;
|
|
||||||
case MESA_SHADER_TESS_EVAL:
|
|
||||||
/* The tess eval shader uses ldg, which takes dword offsets. */
|
|
||||||
factor = 1;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
unreachable("bad shader stage");
|
|
||||||
}
|
|
||||||
|
|
||||||
nir_foreach_variable(in_var, &consumer->shader->nir->inputs) {
|
|
||||||
nir_foreach_variable(out_var, &producer->shader->nir->outputs) {
|
|
||||||
if (in_var->data.location == out_var->data.location) {
|
|
||||||
locs[in_var->data.driver_location] =
|
|
||||||
producer->shader->output_loc[out_var->data.driver_location] * factor;
|
|
||||||
|
|
||||||
debug_assert(num_loc <= in_var->data.driver_location + 1);
|
|
||||||
num_loc = in_var->data.driver_location + 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return num_loc;
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
void
|
||||||
ir3_emit_link_map(struct fd_screen *screen,
|
ir3_emit_link_map(struct fd_screen *screen,
|
||||||
const struct ir3_shader_variant *producer,
|
const struct ir3_shader_variant *producer,
|
||||||
|
@ -457,7 +421,7 @@ ir3_emit_link_map(struct fd_screen *screen,
|
||||||
uint32_t base = const_state->offsets.primitive_map;
|
uint32_t base = const_state->offsets.primitive_map;
|
||||||
uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
|
uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
|
||||||
|
|
||||||
num_loc = link_geometry_stages(producer, v, patch_locs);
|
num_loc = ir3_link_geometry_stages(producer, v, patch_locs);
|
||||||
|
|
||||||
int size = DIV_ROUND_UP(num_loc, 4);
|
int size = DIV_ROUND_UP(num_loc, 4);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue