radv: move lots of index related things into the bind.
This just moves lots of stuff to the bind stage rather than dealing with it in the draw stage. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1987,12 +1987,16 @@ void radv_CmdBindIndexBuffer(
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VkIndexType indexType)
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VkIndexType indexType)
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{
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
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cmd_buffer->state.index_buffer = radv_buffer_from_handle(buffer);
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cmd_buffer->state.index_offset = offset;
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cmd_buffer->state.index_type = indexType; /* vk matches hw */
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cmd_buffer->state.index_type = indexType; /* vk matches hw */
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cmd_buffer->state.index_va = cmd_buffer->device->ws->buffer_get_va(index_buffer->bo);
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cmd_buffer->state.index_va += index_buffer->offset + offset;
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int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
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cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, cmd_buffer->state.index_buffer->bo, 8);
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cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
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}
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}
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@ -2639,12 +2643,6 @@ void radv_CmdDraw(
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radv_cmd_buffer_trace_emit(cmd_buffer);
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radv_cmd_buffer_trace_emit(cmd_buffer);
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}
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}
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static
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uint32_t radv_get_max_index_count(struct radv_cmd_buffer *cmd_buffer) {
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int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
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return (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) >> index_size_shift;
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}
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void radv_CmdDrawIndexed(
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void radv_CmdDrawIndexed(
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VkCommandBuffer commandBuffer,
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VkCommandBuffer commandBuffer,
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uint32_t indexCount,
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uint32_t indexCount,
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@ -2655,7 +2653,6 @@ void radv_CmdDrawIndexed(
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{
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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int index_size = cmd_buffer->state.index_type ? 4 : 2;
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int index_size = cmd_buffer->state.index_type ? 4 : 2;
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uint32_t index_max_size = radv_get_max_index_count(cmd_buffer);
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uint64_t index_va;
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uint64_t index_va;
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radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
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radv_cmd_buffer_flush_state(cmd_buffer, true, (instanceCount > 1), false, indexCount);
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@ -2681,10 +2678,10 @@ void radv_CmdDrawIndexed(
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
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radeon_emit(cmd_buffer->cs, instanceCount);
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radeon_emit(cmd_buffer->cs, instanceCount);
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index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
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index_va = cmd_buffer->state.index_va;
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index_va += firstIndex * index_size + cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
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index_va += firstIndex * index_size;
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
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radeon_emit(cmd_buffer->cs, index_max_size);
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radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
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radeon_emit(cmd_buffer->cs, index_va);
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radeon_emit(cmd_buffer->cs, index_va);
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radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
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radeon_emit(cmd_buffer->cs, (index_va >> 32UL) & 0xFF);
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radeon_emit(cmd_buffer->cs, indexCount);
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radeon_emit(cmd_buffer->cs, indexCount);
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@ -2780,12 +2777,10 @@ radv_cmd_draw_indexed_indirect_count(
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uint32_t stride)
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uint32_t stride)
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{
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{
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
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uint32_t index_max_size = radv_get_max_index_count(cmd_buffer);
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uint64_t index_va;
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uint64_t index_va;
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radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
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radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
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index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo);
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index_va = cmd_buffer->state.index_va;
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index_va += cmd_buffer->state.index_buffer->offset + cmd_buffer->state.index_offset;
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
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MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 21);
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@ -2797,7 +2792,7 @@ radv_cmd_draw_indexed_indirect_count(
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radeon_emit(cmd_buffer->cs, index_va >> 32);
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radeon_emit(cmd_buffer->cs, index_va >> 32);
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
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radeon_emit(cmd_buffer->cs, index_max_size);
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radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
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radv_emit_indirect_draw(cmd_buffer, buffer, offset,
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radv_emit_indirect_draw(cmd_buffer, buffer, offset,
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countBuffer, countBufferOffset, maxDrawCount, stride, true);
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countBuffer, countBufferOffset, maxDrawCount, stride, true);
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@ -764,9 +764,9 @@ struct radv_cmd_state {
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struct radv_descriptor_set * descriptors[MAX_SETS];
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struct radv_descriptor_set * descriptors[MAX_SETS];
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struct radv_attachment_state * attachments;
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struct radv_attachment_state * attachments;
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VkRect2D render_area;
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VkRect2D render_area;
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struct radv_buffer * index_buffer;
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uint32_t index_type;
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uint32_t index_type;
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uint32_t index_offset;
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uint64_t index_va;
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uint32_t max_index_count;
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int32_t last_primitive_reset_en;
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int32_t last_primitive_reset_en;
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uint32_t last_primitive_reset_index;
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uint32_t last_primitive_reset_index;
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enum radv_cmd_flush_bits flush_bits;
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enum radv_cmd_flush_bits flush_bits;
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