radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast
PA_SC_AA_CONFIG might be updated when conversative rasterization is enabled. Because the driver only re-emits the multisample state if the number of samples is different, that register value might not be updated correctly. Found by inspection, doesn't fix anything known. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -865,7 +865,6 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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{
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int num_samples = pipeline->graphics.ms.num_samples;
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struct radv_multisample_state *ms = &pipeline->graphics.ms;
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struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
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if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.needs_sample_positions)
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@ -874,17 +873,8 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
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if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
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return;
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, 1);
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radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
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radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
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/* GFX9: Flush DFSM when the AA mode changes. */
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if (cmd_buffer->device->dfsm_allowed) {
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radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
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}
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cmd_buffer->state.context_roll_without_scissor_emitted = true;
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}
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@ -3651,6 +3651,7 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
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radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
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radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
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radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
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radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
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/* The exclusion bits can be set to improve rasterization efficiency
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* if no sample lies on the pixel boundary (-8 sample offset). It's
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@ -3660,6 +3661,12 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
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radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
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S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
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S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
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/* GFX9: Flush DFSM when the AA mode changes. */
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if (pipeline->device->dfsm_allowed) {
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radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
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}
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}
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static void
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