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iris: Fix aux usage of depth buffer prepare/finish 

Prepare/finish a framebuffer's depth buffer with the aux usage that's
appropriate for the given miplevel instead of wrongly assuming that
compression is always enabled. Enables code simplifications later on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8853>
This commit is contained in:
Nanley Chery 2020-12-16 14:57:14 -08:00 committed by Marge Bot
parent 7170479475
commit 0079b8543a
4 changed files with 12 additions and 38 deletions
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3
src/gallium/drivers/iris/iris_context.h
View File

@ -707,6 +707,9 @@ struct iris_context {
*/
enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
/** Aux usage of the fb's depth buffer (which may or may not exist). */
enum isl_aux_usage hiz_usage;
enum gen_urb_deref_block_size urb_deref_block_size;
/** Are depth writes enabled? (Depth buffer may or may not exist.) */

37
src/gallium/drivers/iris/iris_resolve.c
View File

@ -201,10 +201,9 @@ iris_predraw_resolve_framebuffer(struct iris_context *ice,
zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
if (z_res) {
iris_resource_prepare_depth(ice, batch, z_res,
zs_surf->u.tex.level,
zs_surf->u.tex.first_layer,
num_layers);
iris_resource_prepare_render(ice, z_res, zs_surf->u.tex.level,
zs_surf->u.tex.first_layer,
num_layers, ice->state.hiz_usage);
iris_emit_buffer_barrier_for(batch, z_res->bo,
IRIS_DOMAIN_DEPTH_WRITE);
}
@ -293,10 +292,10 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
if (z_res) {
if (may_have_resolved_depth) {
iris_resource_finish_depth(ice, z_res, zs_surf->u.tex.level,
zs_surf->u.tex.first_layer, num_layers,
ice->state.depth_writes_enabled);
if (may_have_resolved_depth && ice->state.depth_writes_enabled) {
iris_resource_finish_render(ice, z_res, zs_surf->u.tex.level,
zs_surf->u.tex.first_layer,
num_layers, ice->state.hiz_usage);
}
}
@ -1042,25 +1041,3 @@ iris_resource_finish_render(struct iris_context *ice,
iris_resource_finish_write(ice, res, level, start_layer, layer_count,
aux_usage);
}
void
iris_resource_prepare_depth(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count)
{
iris_resource_prepare_access(ice, res, level, 1, start_layer,
layer_count, res->aux.usage, !!res->aux.bo);
}
void
iris_resource_finish_depth(struct iris_context *ice,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
bool depth_written)
{
if (depth_written) {
iris_resource_finish_write(ice, res, level, start_layer, layer_count,
res->aux.usage);
}
}

8
src/gallium/drivers/iris/iris_resource.h
View File

@ -513,12 +513,4 @@ void iris_resource_finish_render(struct iris_context *ice,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
enum isl_aux_usage aux_usage);
void iris_resource_prepare_depth(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count);
void iris_resource_finish_depth(struct iris_context *ice,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
bool depth_written);
#endif

2
src/gallium/drivers/iris/iris_state.c
View File

@ -3167,6 +3167,8 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
info.hiz_surf = &zres->aux.surf;
info.hiz_address = zres->aux.bo->gtt_offset + zres->aux.offset;
}
ice->state.hiz_usage = info.hiz_usage;
}
if (stencil_res) {