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anv: fix some multisample lines_wide CTS tests 

We can use a better algorithm from ICL and onward by setting a chicken
bit, but prior to that we need to resort to disabling rectangular lines.
Since we don't support strictLines anyway, this shouldn't be a major
issue.

Closes #2833
Fixes dEQP-VK.rasterization.interpolation_multisample_*_bit.*lines_wide

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11672>
This commit is contained in:
Iván Briano 2021-04-22 11:14:02 -07:00 committed by Marge Bot
parent f40a08d25c
commit 004fcfe698
8 changed files with 49 additions and 7 deletions
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5
src/intel/genxml/gen11.xml
View File

@ -6873,6 +6873,11 @@
<field name="MFX Pipeline Command Flush" start="51" end="51" type="bool"/>
</instruction>
<register name="3D_CHICKEN3" length="1" num="0x2090">
<field name="AA Line Quality Fix" start="5" end="5" type="bool"/>
<field name="AA Line Quality Fix Mask" start="21" end="21" type="bool"/>
</register>
<register name="BCS_INSTDONE" length="1" num="0x2206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="Blitter IDLE" start="1" end="1" type="bool" default="1"/>

5
src/intel/genxml/gen12.xml
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@ -7061,6 +7061,11 @@
<field name="MFX Pipeline Command Flush" start="51" end="51" type="bool"/>
</instruction>
<register name="3D_CHICKEN3" length="1" num="0x2090">
<field name="AA Line Quality Fix" start="5" end="5" type="bool"/>
<field name="AA Line Quality Fix Mask" start="21" end="21" type="bool"/>
</register>
<register name="BCS_INSTDONE" length="1" num="0x2206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="Blitter IDLE" start="1" end="1" type="bool" default="1"/>

5
src/intel/genxml/gen125.xml
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@ -7025,6 +7025,11 @@
<field name="Per Sample Blend Opt Disable Mask" start="27" end="27" type="bool"/>
</register>
<register name="CHICKEN_RASTER_1" length="1" num="0x6204">
<field name="AA Line Quality Fix" start="5" end="5" type="bool"/>
<field name="AA Line Quality Fix Mask" start="21" end="21" type="bool"/>
</register>
<register name="CL_INVOCATION_COUNT" length="2" num="0x2338">
<field name="CL Invocation Count Report" start="0" end="63" type="uint"/>
</register>

11
src/intel/vulkan/anv_device.c
View File

@ -2011,11 +2011,12 @@ void anv_GetPhysicalDeviceProperties(
.maxCombinedClipAndCullDistances = 8,
.discreteQueuePriorities = 2,
.pointSizeRange = { 0.125, 255.875 },
.lineWidthRange = {
0.0,
(devinfo->ver >= 9 || devinfo->is_cherryview) ?
2047.9921875 : 7.9921875,
},
/* While SKL and up support much wider lines than we are setting here,
* in practice we run into conformance issues if we go past this limit.
* Since the Windows driver does the same, it's probably fair to assume
* that no one needs more than this.
*/
.lineWidthRange = { 0.0, 8.0 },
.pointSizeGranularity = (1.0 / 8.0),
.lineWidthGranularity = (1.0 / 128.0),
.strictLines = false,

1
src/intel/vulkan/anv_genX.h
View File

@ -130,6 +130,7 @@ void genX(cmd_emit_timestamp)(struct anv_batch *batch,
void
genX(rasterization_mode)(VkPolygonMode raster_mode,
VkLineRasterizationModeEXT line_mode,
float line_width,
uint32_t *api_mode,
bool *msaa_rasterization_enable);

11
src/intel/vulkan/genX_pipeline.c
View File

@ -580,6 +580,7 @@ vk_conservative_rasterization_mode(const VkPipelineRasterizationStateCreateInfo
void
genX(rasterization_mode)(VkPolygonMode raster_mode,
VkLineRasterizationModeEXT line_mode,
float line_width,
uint32_t *api_mode,
bool *msaa_rasterization_enable)
{
@ -599,7 +600,16 @@ genX(rasterization_mode)(VkPolygonMode raster_mode,
switch (line_mode) {
case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT:
*api_mode = DX100;
#if GFX_VER <= 9
/* Prior to ICL, the algorithm the HW uses to draw wide lines
* doesn't quite match what the CTS expects, at least for rectangular
* lines, so we set this to false here, making it draw parallelograms
* instead, which work well enough.
*/
*msaa_rasterization_enable = line_width < 1.0078125;
#else
*msaa_rasterization_enable = true;
#endif
break;
case VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT:
@ -694,6 +704,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
#if GFX_VER >= 8
if (!dynamic_primitive_topology)
genX(rasterization_mode)(raster_mode, pipeline->line_mode,
rs_info->lineWidth,
&raster.APIMode,
&raster.DXMultisampleRasterizationEnable);

14
src/intel/vulkan/genX_state.c
View File

@ -256,6 +256,20 @@ init_render_queue_state(struct anv_queue *queue)
cc1.ReplayMode = MidcmdbufferPreemption;
cc1.ReplayModeMask = true;
}
#if GFX_VERx10 < 125
#define AA_LINE_QUALITY_REG GENX(3D_CHICKEN3)
#else
#define AA_LINE_QUALITY_REG GENX(CHICKEN_RASTER_1)
#endif
/* Enable the new line drawing algorithm that produces higher quality
* lines.
*/
anv_batch_write_reg(&batch, AA_LINE_QUALITY_REG, c3) {
c3.AALineQualityFix = true;
c3.AALineQualityFixMask = true;
}
#endif
#if GFX_VER == 12

4
src/intel/vulkan/gfx8_cmd_buffer.c
View File

@ -478,8 +478,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
primitive_topology);
genX(rasterization_mode)(
dynamic_raster_mode, pipeline->line_mode, &api_mode,
&msaa_raster_enable);
dynamic_raster_mode, pipeline->line_mode, d->line_width,
&api_mode, &msaa_raster_enable);
aa_enable =
anv_rasterization_aa_mode(dynamic_raster_mode,