i965/fs: Make half() divide the register width by 2 and use it more
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -1322,6 +1322,7 @@ fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
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fs_reg *
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fs_visitor::emit_samplepos_setup()
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{
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fs_inst *inst;
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assert(brw->gen >= 6);
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this->current_annotation = "compute sample position";
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@ -1345,8 +1346,10 @@ fs_visitor::emit_samplepos_setup()
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stride(retype(brw_vec1_grf(payload.sample_pos_reg, 0),
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BRW_REGISTER_TYPE_B), 16, 8, 2);
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fs_inst *inst = emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
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if (dispatch_width == 16) {
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if (dispatch_width == 8) {
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emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
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} else {
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inst = emit(MOV(half(int_sample_x, 0), fs_reg(sample_pos_reg)));
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inst->force_uncompressed = true;
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inst = emit(MOV(half(int_sample_x, 1),
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fs_reg(suboffset(sample_pos_reg, 16))));
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@ -1355,8 +1358,11 @@ fs_visitor::emit_samplepos_setup()
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/* Compute gl_SamplePosition.x */
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compute_sample_position(pos, int_sample_x);
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pos = offset(pos, 1);
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inst = emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
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if (dispatch_width == 16) {
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if (dispatch_width == 8) {
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emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
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} else {
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inst = emit(MOV(half(int_sample_y, 0),
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fs_reg(suboffset(sample_pos_reg, 1))));
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inst->force_uncompressed = true;
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inst = emit(MOV(half(int_sample_y, 1),
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fs_reg(suboffset(sample_pos_reg, 17))));
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@ -145,10 +145,12 @@ byte_offset(fs_reg reg, unsigned delta)
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* Note: this also works if \c reg represents a SIMD16 pair of registers.
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*/
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static inline fs_reg
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half(const fs_reg ®, unsigned idx)
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half(fs_reg reg, unsigned idx)
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{
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assert(idx < 2);
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assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
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assert(reg.width == 16);
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reg.width = 8;
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return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
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}
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