winsys/amdgpu: enable DCC for mipmapped textures
Also add dcc_fast_clear_size for clearing only the necessary subset of DCC. For no AA, it's equal to the size of the whole DCC level. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -931,8 +931,11 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
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rtex->dcc_offset, rtex->surface.dcc_size,
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rtex->surface.dcc_alignment);
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for (i = 0; i <= rtex->surface.last_level; i++)
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fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n",
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i, rtex->surface.level[i].dcc_offset);
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fprintf(f, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64", "
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"fast_clear_size=%"PRIu64"\n",
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i, rtex->surface.level[i].dcc_enabled,
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rtex->surface.level[i].dcc_offset,
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rtex->surface.level[i].dcc_fast_clear_size);
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}
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for (i = 0; i <= rtex->surface.last_level; i++)
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@ -1865,7 +1868,8 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
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vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed);
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rctx->clear_buffer(&rctx->b, &tex->resource.b.b,
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tex->dcc_offset, tex->surface.dcc_size,
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tex->dcc_offset,
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tex->surface.level[0].dcc_fast_clear_size,
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reset_value, R600_COHERENCY_CB_META);
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if (clear_words_needed)
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@ -360,6 +360,7 @@ struct radeon_surf_level {
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uint32_t pitch_bytes;
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uint32_t mode;
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uint64_t dcc_offset;
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uint64_t dcc_fast_clear_size;
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bool dcc_enabled;
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};
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@ -230,7 +230,9 @@ static int compute_level(struct amdgpu_winsys *ws,
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surf_level->dcc_offset = 0;
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surf_level->dcc_enabled = false;
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if (AddrSurfInfoIn->flags.dccCompatible) {
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/* The previous level's flag tells us if we can use DCC for this level. */
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if (AddrSurfInfoIn->flags.dccCompatible &&
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(level == 0 || AddrDccOut->subLvlCompressible)) {
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AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
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AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
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AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
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@ -243,14 +245,11 @@ static int compute_level(struct amdgpu_winsys *ws,
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if (ret == ADDR_OK) {
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surf_level->dcc_offset = surf->dcc_size;
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surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
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surf_level->dcc_enabled = true;
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surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
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surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
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} else {
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surf->dcc_size = 0;
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}
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} else {
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surf->dcc_size = 0;
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}
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return 0;
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@ -344,11 +343,19 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
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AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
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AddrSurfInfoIn.flags.degrade4Space = 1;
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/* DCC notes:
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* - If we add MSAA support, keep in mind that CB can't decompress 8bpp
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* with samples >= 4.
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* - Mipmapped array textures have low performance (discovered by a closed
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* driver team).
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*/
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AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
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!(surf->flags & RADEON_SURF_SCANOUT) &&
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!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
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!compressed && AddrDccIn.numSamples <= 1 &&
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surf->last_level == 0;
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((surf->array_size == 1 && surf->npix_z == 1) ||
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surf->last_level == 0);
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AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
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AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
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@ -445,6 +452,16 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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}
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}
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/* Recalculate the whole DCC miptree size including disabled levels.
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* This is what addrlib does, but calling addrlib would be a lot more
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* complicated.
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*/
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if (surf->dcc_size && surf->last_level > 0) {
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surf->dcc_size = align64(surf->bo_size >> 8,
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ws->info.pipe_interleave_bytes *
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ws->info.num_tile_pipes);
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}
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return 0;
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}
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