2021-04-11 21:01:47 +01:00
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/*
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* Copyright (C) 2021 Alyssa Rosenzweig <alyssa@rosenzweig.io>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "agx_compiler.h"
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#include "agx_builder.h"
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/* Trivial register allocator that never frees anything.
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*
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* TODO: Write a real register allocator.
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* TODO: Handle phi nodes.
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*/
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2021-06-19 19:33:12 +01:00
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/** Returns number of registers written by an instruction */
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2021-06-19 18:23:25 +01:00
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static unsigned
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2021-06-19 19:33:12 +01:00
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agx_write_registers(agx_instr *I, unsigned d)
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{
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unsigned size = I->dest[d].size == AGX_SIZE_32 ? 2 : 1;
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2021-06-19 18:23:25 +01:00
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switch (I->op) {
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case AGX_OPCODE_LD_VARY:
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case AGX_OPCODE_DEVICE_LOAD:
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case AGX_OPCODE_TEXTURE_SAMPLE:
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case AGX_OPCODE_LD_TILE:
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return 8;
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2021-06-19 18:23:25 +01:00
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case AGX_OPCODE_LD_VARY_FLAT:
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return 6;
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2021-06-19 18:23:25 +01:00
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default:
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2021-06-19 19:33:12 +01:00
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return size;
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2021-06-19 18:23:25 +01:00
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}
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}
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2021-04-11 21:01:47 +01:00
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void
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agx_ra(agx_context *ctx)
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{
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unsigned *alloc = calloc(ctx->alloc, sizeof(unsigned));
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unsigned usage = 6*2;
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agx_foreach_instr_global_safe(ctx, ins) {
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/* Lower away RA pseudo-instructions */
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if (ins->op == AGX_OPCODE_P_COMBINE) {
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/* TODO: Optimize out the moves! */
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unsigned components = 0;
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for (unsigned i = 0; i < 4; ++i) {
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if (!agx_is_null(ins->src[i]))
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components = i + 1;
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}
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unsigned size = ins->dest[0].size == AGX_SIZE_32 ? 2 : 1;
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if (size == 2 && usage & 1) usage++;
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unsigned base = usage;
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assert(ins->dest[0].type == AGX_INDEX_NORMAL);
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alloc[ins->dest[0].value] = base;
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usage += (components * size);
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/* Move the sources */
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agx_builder b = agx_init_builder(ctx, agx_after_instr(ins));
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for (unsigned i = 0; i < 4; ++i) {
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if (agx_is_null(ins->src[i])) continue;
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assert(ins->src[0].type == AGX_INDEX_NORMAL);
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agx_mov_to(&b, agx_register(base + (i * size), ins->dest[0].size),
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agx_register(alloc[ins->src[i].value], ins->src[0].size));
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}
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/* We've lowered away, delete the old */
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agx_remove_instruction(ins);
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continue;
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} else if (ins->op == AGX_OPCODE_P_EXTRACT) {
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assert(ins->dest[0].type == AGX_INDEX_NORMAL);
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assert(ins->src[0].type == AGX_INDEX_NORMAL);
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assert(ins->dest[0].size == ins->src[0].size);
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unsigned size = ins->dest[0].size == AGX_SIZE_32 ? 2 : 1;
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alloc[ins->dest[0].value] = alloc[ins->src[0].value] + (size * ins->imm);
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agx_remove_instruction(ins);
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continue;
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}
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agx_foreach_src(ins, s) {
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if (ins->src[s].type == AGX_INDEX_NORMAL) {
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unsigned v = alloc[ins->src[s].value];
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ins->src[s] = agx_replace_index(ins->src[s], agx_register(v, ins->src[s].size));
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}
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}
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agx_foreach_dest(ins, d) {
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if (ins->dest[d].type == AGX_INDEX_NORMAL) {
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unsigned size = ins->dest[d].size == AGX_SIZE_32 ? 2 : 1;
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if (size == 2 && usage & 1) usage++;
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unsigned v = usage;
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usage += agx_write_registers(ins, d);
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alloc[ins->dest[d].value] = v;
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ins->dest[d] = agx_replace_index(ins->dest[d], agx_register(v, ins->dest[d].size));
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}
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}
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}
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assert(usage < 256 && "dummy RA");
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free(alloc);
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}
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