581 lines
15 KiB
C
581 lines
15 KiB
C
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/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
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/*
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* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "pipe/p_shader_tokens.h"
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#include "util/u_math.h"
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#include "ir3.h"
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#include "ir3_visitor.h"
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/*
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* Register Assignment:
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*
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* NOTE: currently only works on a single basic block.. need to think
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* about how multiple basic blocks are going to get scheduled. But
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* I think I want to re-arrange how blocks work, ie. get rid of the
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* block nesting thing..
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*
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* NOTE: we could do register coalescing (eliminate moves) as part of
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* the RA step.. OTOH I think we need to do scheduling before register
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* assignment. And if we remove a mov that effects scheduling (unless
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* we leave a placeholder nop, which seems lame), so I'm not really
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* sure how practical this is to do both in a single stage. But OTOH
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* I'm not really sure a sane way for the CP stage to realize when it
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* cannot remove a mov due to multi-register constraints..
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*
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*/
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struct ir3_ra_ctx {
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struct ir3_block *block;
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enum shader_t type;
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int cnt;
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bool error;
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};
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struct ir3_ra_assignment {
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int8_t off; /* offset of instruction dst within range */
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uint8_t num; /* number of components for the range */
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};
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static void ra_assign(struct ir3_ra_ctx *ctx,
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struct ir3_instruction *assigner, int num);
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static struct ir3_ra_assignment ra_calc(struct ir3_instruction *instr);
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/*
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* Register Allocation:
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*/
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#define REG(n, wm) (struct ir3_register){ \
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/*.flags = ((so)->half_precision) ? IR3_REG_HALF : 0,*/ \
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.num = (n), \
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.wrmask = TGSI_WRITEMASK_ ## wm, \
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}
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/* check that the register exists, is a GPR and is not special (a0/p0) */
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static struct ir3_register * reg_check(struct ir3_instruction *instr, unsigned n)
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{
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if ((n < instr->regs_count) && reg_gpr(instr->regs[n]))
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return instr->regs[n];
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return NULL;
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}
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static int output_base(struct ir3_ra_ctx *ctx)
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{
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/* ugg, for fragment shader we need to have input at r0.x
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* (or at least if there is a way to configure it, I can't
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* see how because the blob driver always uses r0.x (ie.
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* all zeros)
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*/
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if (ctx->type == SHADER_FRAGMENT)
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return 2;
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return 0;
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}
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/* live means read before written */
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static void compute_liveregs(struct ir3_ra_ctx *ctx,
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struct ir3_instruction *instr, regmask_t *liveregs)
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{
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struct ir3_block *block = instr->block;
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regmask_t written;
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unsigned i, j;
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regmask_init(liveregs);
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regmask_init(&written);
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for (instr = instr->next; instr; instr = instr->next) {
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struct ir3_register *r;
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if (is_meta(instr))
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continue;
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/* check first src's read: */
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for (j = 1; j < instr->regs_count; j++) {
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r = reg_check(instr, j);
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if (r)
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regmask_set_if_not(liveregs, r, &written);
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}
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/* then dst written (if assigned already): */
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if (instr->flags & IR3_INSTR_MARK) {
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r = reg_check(instr, 0);
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if (r)
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regmask_set(&written, r);
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}
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}
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/* be sure to account for output registers too: */
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for (i = 0; i < block->noutputs; i++) {
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struct ir3_register reg = REG(output_base(ctx) + i, X);
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regmask_set_if_not(liveregs, ®, &written);
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}
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}
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/* calculate registers that are clobbered before last use of 'assigner'.
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* This needs to be done backwards, although it could possibly be
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* combined into compute_liveregs(). (Ie. compute_liveregs() could
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* reverse the list, then do this part backwards reversing the list
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* again back to original order.) Otoh, probably I should try to
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* construct a proper interference graph instead.
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*
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* XXX this need to follow the same recursion path that is used for
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* to rename/assign registers (ie. ra_assign_src()).. this is a bit
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* ugly right now, maybe refactor into node iterator sort of things
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* that iterates nodes in the correct order?
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*/
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static bool compute_clobbers(struct ir3_ra_ctx *ctx,
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struct ir3_instruction *instr, struct ir3_instruction *assigner,
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regmask_t *liveregs)
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{
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unsigned i;
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bool live = false, was_live = false;
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if (instr == NULL) {
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struct ir3_block *block = ctx->block;
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/* if at the end, check outputs: */
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for (i = 0; i < block->noutputs; i++)
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if (block->outputs[i] == assigner)
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return true;
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return false;
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}
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for (i = 1; i < instr->regs_count; i++) {
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struct ir3_register *reg = instr->regs[i];
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if ((reg->flags & IR3_REG_SSA) && (reg->instr == assigner)) {
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if (is_meta(instr)) {
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switch (instr->opc) {
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case OPC_META_INPUT:
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// TODO
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assert(0);
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break;
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case OPC_META_FO:
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case OPC_META_FI:
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was_live |= compute_clobbers(ctx, instr->next,
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instr, liveregs);
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break;
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default:
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break;
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}
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}
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live = true;
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break;
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}
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}
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was_live |= compute_clobbers(ctx, instr->next, assigner, liveregs);
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if (was_live && (instr->regs_count > 0) &&
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(instr->flags & IR3_INSTR_MARK) &&
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!is_meta(instr))
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regmask_set(liveregs, instr->regs[0]);
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return live || was_live;
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}
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static int find_available(regmask_t *liveregs, int size)
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{
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unsigned i;
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for (i = 0; i < MAX_REG - size; i++) {
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if (!regmask_get(liveregs, ®(i, X))) {
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unsigned start = i++;
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for (; (i < MAX_REG) && ((i - start) < size); i++)
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if (regmask_get(liveregs, ®(i, X)))
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break;
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if ((i - start) >= size)
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return start;
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}
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}
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assert(0);
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return -1;
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}
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static int alloc_block(struct ir3_ra_ctx *ctx,
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struct ir3_instruction *instr, int size)
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{
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if (!instr) {
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/* special case, allocating shader outputs. At this
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* point, nothing is allocated, just start the shader
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* outputs at r0.x and let compute_liveregs() take
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* care of the rest from here:
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*/
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return 0;
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} else {
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regmask_t liveregs;
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compute_liveregs(ctx, instr, &liveregs);
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// XXX XXX XXX XXX XXX XXX XXX XXX XXX
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// XXX hack.. maybe ra_calc should give us a list of
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// instrs to compute_clobbers() on?
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if (is_meta(instr) && (instr->opc == OPC_META_INPUT) &&
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(instr->regs_count == 1)) {
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unsigned i, base = instr->regs[0]->num & ~0x3;
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for (i = 0; i < 4; i++) {
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struct ir3_instruction *in = ctx->block->inputs[base + i];
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if (in)
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compute_clobbers(ctx, in->next, in, &liveregs);
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}
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} else
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// XXX XXX XXX XXX XXX XXX XXX XXX XXX
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compute_clobbers(ctx, instr->next, instr, &liveregs);
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return find_available(&liveregs, size);
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}
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}
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/*
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* Constraint Calculation:
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*/
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struct ra_calc_visitor {
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struct ir3_visitor base;
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struct ir3_ra_assignment a;
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};
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static inline struct ra_calc_visitor *ra_calc_visitor(struct ir3_visitor *v)
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{
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return (struct ra_calc_visitor *)v;
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}
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/* calculate register assignment for the instruction. If the register
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* written by this instruction is required to be part of a range, to
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* handle other (input/output/sam/bary.f/etc) contiguous register range
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* constraints, that is calculated handled here.
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*/
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static void ra_calc_dst(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_calc_visitor *c = ra_calc_visitor(v);
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if (is_tex(instr)) {
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c->a.off = 0;
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c->a.num = 4;
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} else {
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c->a.off = 0;
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c->a.num = 1;
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}
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}
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static void
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ra_calc_dst_shader_input(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_calc_visitor *c = ra_calc_visitor(v);
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struct ir3_block *block = instr->block;
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struct ir3_register *dst = instr->regs[0];
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unsigned base = dst->num & ~0x3;
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unsigned i, num = 0;
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assert(!(dst->flags & IR3_REG_IA));
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/* check what input components we need: */
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for (i = 0; i < 4; i++) {
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unsigned idx = base + i;
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if ((idx < block->ninputs) && block->inputs[idx])
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num = i + 1;
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}
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c->a.off = dst->num - base;
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c->a.num = num;
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}
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static void ra_calc_src_fanin(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_calc_visitor *c = ra_calc_visitor(v);
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unsigned srcn = ir3_instr_regno(instr, reg) - 1;
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c->a.off -= srcn;
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c->a.num += srcn;
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c->a.num = MAX2(c->a.num, instr->regs_count - 1);
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}
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static const struct ir3_visitor_funcs calc_visitor_funcs = {
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.instr = ir3_visit_instr,
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.dst_shader_input = ra_calc_dst_shader_input,
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.dst_fanout = ra_calc_dst,
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.dst_fanin = ra_calc_dst,
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.dst = ra_calc_dst,
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.src_fanout = ir3_visit_reg,
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.src_fanin = ra_calc_src_fanin,
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.src = ir3_visit_reg,
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};
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static struct ir3_ra_assignment ra_calc(struct ir3_instruction *assigner)
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{
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struct ra_calc_visitor v = {
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.base.funcs = &calc_visitor_funcs,
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};
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ir3_visit_instr(&v.base, assigner);
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return v.a;
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}
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/*
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* Register Assignment:
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*/
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struct ra_assign_visitor {
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struct ir3_visitor base;
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struct ir3_ra_ctx *ctx;
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int num;
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};
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static inline struct ra_assign_visitor *ra_assign_visitor(struct ir3_visitor *v)
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{
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return (struct ra_assign_visitor *)v;
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}
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static void ra_assign_reg(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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reg->flags &= ~IR3_REG_SSA;
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reg->num = a->num;
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}
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static void ra_assign_dst_shader_input(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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unsigned i, base = reg->num & ~0x3;
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int off = base - reg->num;
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ra_assign_reg(v, instr, reg);
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reg->flags |= IR3_REG_IA;
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/* trigger assignment of all our companion input components: */
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for (i = 0; i < 4; i++) {
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struct ir3_instruction *in = instr->block->inputs[i+base];
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if (in && is_meta(in) && (in->opc == OPC_META_INPUT))
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ra_assign(a->ctx, in, a->num + off + i);
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}
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}
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static void ra_assign_dst_fanout(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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struct ir3_register *src = instr->regs[1];
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ra_assign_reg(v, instr, reg);
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if (src->flags & IR3_REG_SSA)
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ra_assign(a->ctx, src->instr, a->num - instr->fo.off);
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}
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static void ra_assign_src_fanout(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
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{
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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ra_assign_reg(v, instr, reg);
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ra_assign(a->ctx, instr, a->num + instr->fo.off);
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}
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static void ra_assign_src_fanin(struct ir3_visitor *v,
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struct ir3_instruction *instr, struct ir3_register *reg)
|
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{
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struct ra_assign_visitor *a = ra_assign_visitor(v);
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unsigned j, srcn = ir3_instr_regno(instr, reg) - 1;
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ra_assign_reg(v, instr, reg);
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ra_assign(a->ctx, instr, a->num - srcn);
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for (j = 1; j < instr->regs_count; j++) {
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struct ir3_register *reg = instr->regs[j];
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if (reg->flags & IR3_REG_SSA) /* could be renamed already */
|
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ra_assign(a->ctx, reg->instr, a->num - srcn + j - 1);
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}
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||
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}
|
||
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|
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|
static const struct ir3_visitor_funcs assign_visitor_funcs = {
|
||
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.instr = ir3_visit_instr,
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.dst_shader_input = ra_assign_dst_shader_input,
|
||
|
.dst_fanout = ra_assign_dst_fanout,
|
||
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.dst_fanin = ra_assign_reg,
|
||
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.dst = ra_assign_reg,
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||
|
.src_fanout = ra_assign_src_fanout,
|
||
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.src_fanin = ra_assign_src_fanin,
|
||
|
.src = ra_assign_reg,
|
||
|
};
|
||
|
|
||
|
static void ra_assign(struct ir3_ra_ctx *ctx,
|
||
|
struct ir3_instruction *assigner, int num)
|
||
|
{
|
||
|
struct ra_assign_visitor v = {
|
||
|
.base.funcs = &assign_visitor_funcs,
|
||
|
.ctx = ctx,
|
||
|
.num = num,
|
||
|
};
|
||
|
|
||
|
/* if we've already visited this instruction, bail now: */
|
||
|
if (ir3_instr_check_mark(assigner)) {
|
||
|
debug_assert(assigner->regs[0]->num == num);
|
||
|
if (assigner->regs[0]->num != num) {
|
||
|
/* impossible situation, should have been resolved
|
||
|
* at an earlier stage by inserting extra mov's:
|
||
|
*/
|
||
|
ctx->error = true;
|
||
|
}
|
||
|
return;
|
||
|
}
|
||
|
|
||
|
ir3_visit_instr(&v.base, assigner);
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
*
|
||
|
*/
|
||
|
|
||
|
static void ir3_instr_ra(struct ir3_ra_ctx *ctx,
|
||
|
struct ir3_instruction *instr)
|
||
|
{
|
||
|
struct ir3_ra_assignment a;
|
||
|
unsigned num;
|
||
|
|
||
|
/* skip over nop's */
|
||
|
if (instr->regs_count == 0)
|
||
|
return;
|
||
|
|
||
|
/* if we've already visited this instruction, bail now: */
|
||
|
if (instr->flags & IR3_INSTR_MARK)
|
||
|
return;
|
||
|
|
||
|
/* allocate register(s): */
|
||
|
a = ra_calc(instr);
|
||
|
num = alloc_block(ctx, instr, a.num) + a.off;
|
||
|
|
||
|
ra_assign(ctx, instr, num);
|
||
|
}
|
||
|
|
||
|
/* flatten into shader: */
|
||
|
// XXX this should probably be somewhere else:
|
||
|
static void legalize(struct ir3_ra_ctx *ctx, struct ir3_block *block)
|
||
|
{
|
||
|
struct ir3_instruction *n;
|
||
|
struct ir3_shader *shader = block->shader;
|
||
|
struct ir3_instruction *end =
|
||
|
ir3_instr_create(block, 0, OPC_END);
|
||
|
struct ir3_instruction *last_input = NULL;
|
||
|
regmask_t needs_ss;
|
||
|
regmask_t needs_sy;
|
||
|
|
||
|
regmask_init(&needs_ss);
|
||
|
regmask_init(&needs_sy);
|
||
|
|
||
|
shader->instrs_count = 0;
|
||
|
|
||
|
for (n = block->head; n; n = n->next) {
|
||
|
unsigned i;
|
||
|
|
||
|
if (is_meta(n))
|
||
|
continue;
|
||
|
|
||
|
for (i = 1; i < n->regs_count; i++) {
|
||
|
struct ir3_register *reg = n->regs[i];
|
||
|
|
||
|
if (is_gpr(reg)) {
|
||
|
|
||
|
/* TODO: we probably only need (ss) for alu
|
||
|
* instr consuming sfu result.. need to make
|
||
|
* some tests for both this and (sy)..
|
||
|
*/
|
||
|
if (regmask_get(&needs_ss, reg)) {
|
||
|
n->flags |= IR3_INSTR_SS;
|
||
|
regmask_init(&needs_ss);
|
||
|
}
|
||
|
|
||
|
if (regmask_get(&needs_sy, reg)) {
|
||
|
n->flags |= IR3_INSTR_SY;
|
||
|
regmask_init(&needs_sy);
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
shader->instrs[shader->instrs_count++] = n;
|
||
|
|
||
|
if (is_sfu(n))
|
||
|
regmask_set(&needs_ss, n->regs[0]);
|
||
|
if (is_tex(n))
|
||
|
regmask_set(&needs_sy, n->regs[0]);
|
||
|
if (is_input(n))
|
||
|
last_input = n;
|
||
|
}
|
||
|
|
||
|
if (last_input)
|
||
|
last_input->regs[0]->flags |= IR3_REG_EI;
|
||
|
|
||
|
shader->instrs[shader->instrs_count++] = end;
|
||
|
|
||
|
shader->instrs[0]->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
|
||
|
}
|
||
|
|
||
|
static int block_ra(struct ir3_ra_ctx *ctx, struct ir3_block *block)
|
||
|
{
|
||
|
struct ir3_instruction *n;
|
||
|
|
||
|
if (!block->parent) {
|
||
|
unsigned i;
|
||
|
int base, off = output_base(ctx);
|
||
|
|
||
|
base = alloc_block(ctx, NULL, block->noutputs + off);
|
||
|
|
||
|
for (i = 0; i < block->noutputs; i++)
|
||
|
if (block->outputs[i])
|
||
|
ra_assign(ctx, block->outputs[i], base + i + off);
|
||
|
|
||
|
if (ctx->type == SHADER_FRAGMENT) {
|
||
|
for (i = 0; i < block->ninputs; i++)
|
||
|
if (block->inputs[i])
|
||
|
ra_assign(ctx, block->inputs[i], base + i);
|
||
|
} else {
|
||
|
for (i = 0; i < block->ninputs; i++)
|
||
|
if (block->inputs[i])
|
||
|
ir3_instr_ra(ctx, block->inputs[i]);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
/* then loop over instruction list and assign registers:
|
||
|
*/
|
||
|
n = block->head;
|
||
|
while (n) {
|
||
|
ir3_instr_ra(ctx, n);
|
||
|
if (ctx->error)
|
||
|
return -1;
|
||
|
n = n->next;
|
||
|
}
|
||
|
|
||
|
legalize(ctx, block);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int ir3_block_ra(struct ir3_block *block, enum shader_t type)
|
||
|
{
|
||
|
struct ir3_ra_ctx ctx = {
|
||
|
.block = block,
|
||
|
.type = type,
|
||
|
};
|
||
|
ir3_shader_clear_mark(block->shader);
|
||
|
return block_ra(&ctx, block);
|
||
|
}
|