2015-04-16 18:41:33 +01:00
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/*
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* Copyright © 2011 Red Hat All Rights Reserved.
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* Copyright © 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/* Contact:
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* Marek Olšák <maraeo@gmail.com>
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*/
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#include "amdgpu_winsys.h"
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#ifndef NO_ENTRIES
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#define NO_ENTRIES 32
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#endif
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#ifndef NO_MACRO_ENTRIES
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#define NO_MACRO_ENTRIES 16
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#endif
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#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
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#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
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#endif
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static int amdgpu_surface_sanity(const struct radeon_surf *surf)
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{
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unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
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if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
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return -EINVAL;
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/* all dimension must be at least 1 ! */
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if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
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!surf->array_size)
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return -EINVAL;
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if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
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return -EINVAL;
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switch (surf->nsamples) {
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case 1:
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case 2:
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case 4:
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case 8:
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break;
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default:
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return -EINVAL;
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}
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switch (type) {
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case RADEON_SURF_TYPE_1D:
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if (surf->npix_y > 1)
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return -EINVAL;
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/* fall through */
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case RADEON_SURF_TYPE_2D:
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case RADEON_SURF_TYPE_CUBEMAP:
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if (surf->npix_z > 1 || surf->array_size > 1)
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return -EINVAL;
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break;
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case RADEON_SURF_TYPE_3D:
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if (surf->array_size > 1)
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return -EINVAL;
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break;
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case RADEON_SURF_TYPE_1D_ARRAY:
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if (surf->npix_y > 1)
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return -EINVAL;
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/* fall through */
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case RADEON_SURF_TYPE_2D_ARRAY:
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if (surf->npix_z > 1)
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return -EINVAL;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
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{
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return malloc(pInput->sizeInBytes);
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}
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static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
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{
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free(pInput->pVirtAddr);
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return ADDR_OK;
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}
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ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
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{
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ADDR_CREATE_INPUT addrCreateInput = {0};
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ADDR_CREATE_OUTPUT addrCreateOutput = {0};
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ADDR_REGISTER_VALUE regValue = {0};
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ADDR_CREATE_FLAGS createFlags = {{0}};
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ADDR_E_RETURNCODE addrRet;
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addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
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addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
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regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
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regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
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regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
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regValue.backendDisables = ws->amdinfo.backend_disable[0];
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regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
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2015-12-04 04:34:33 +00:00
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regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
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2015-04-16 18:41:33 +01:00
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regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
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2015-12-04 04:34:33 +00:00
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regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
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2015-04-16 18:41:33 +01:00
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createFlags.value = 0;
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createFlags.useTileIndex = 1;
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createFlags.degradeBaseLevel = 1;
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addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
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addrCreateInput.chipFamily = ws->family;
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addrCreateInput.chipRevision = ws->rev_id;
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addrCreateInput.createFlags = createFlags;
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addrCreateInput.callbacks.allocSysMem = allocSysMem;
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addrCreateInput.callbacks.freeSysMem = freeSysMem;
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addrCreateInput.callbacks.debugPrint = 0;
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addrCreateInput.regValue = regValue;
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addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
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if (addrRet != ADDR_OK)
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return NULL;
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return addrCreateOutput.hLib;
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}
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static int compute_level(struct amdgpu_winsys *ws,
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struct radeon_surf *surf, bool is_stencil,
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unsigned level, unsigned type, bool compressed,
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ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
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2015-10-20 23:10:36 +01:00
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
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ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
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ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
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2015-04-16 18:41:33 +01:00
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{
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struct radeon_surf_level *surf_level;
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ADDR_E_RETURNCODE ret;
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AddrSurfInfoIn->mipLevel = level;
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AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
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AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
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if (type == RADEON_SURF_TYPE_3D)
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AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
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else if (type == RADEON_SURF_TYPE_CUBEMAP)
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AddrSurfInfoIn->numSlices = 6;
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else
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AddrSurfInfoIn->numSlices = surf->array_size;
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if (level > 0) {
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/* Set the base level pitch. This is needed for calculation
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* of non-zero levels. */
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if (is_stencil)
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AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
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else
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AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
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/* Convert blocks to pixels for compressed formats. */
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if (compressed)
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AddrSurfInfoIn->basePitch *= surf->blk_w;
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}
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ret = AddrComputeSurfaceInfo(ws->addrlib,
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AddrSurfInfoIn,
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AddrSurfInfoOut);
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if (ret != ADDR_OK) {
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return ret;
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}
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surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
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2016-04-10 15:48:55 +01:00
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surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
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2015-04-16 18:41:33 +01:00
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surf_level->slice_size = AddrSurfInfoOut->sliceSize;
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surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
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surf_level->npix_x = u_minify(surf->npix_x, level);
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surf_level->npix_y = u_minify(surf->npix_y, level);
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surf_level->npix_z = u_minify(surf->npix_z, level);
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surf_level->nblk_x = AddrSurfInfoOut->pitch;
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surf_level->nblk_y = AddrSurfInfoOut->height;
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if (type == RADEON_SURF_TYPE_3D)
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surf_level->nblk_z = AddrSurfInfoOut->depth;
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else
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surf_level->nblk_z = 1;
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switch (AddrSurfInfoOut->tileMode) {
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case ADDR_TM_LINEAR_ALIGNED:
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surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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break;
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case ADDR_TM_1D_TILED_THIN1:
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surf_level->mode = RADEON_SURF_MODE_1D;
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break;
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case ADDR_TM_2D_TILED_THIN1:
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surf_level->mode = RADEON_SURF_MODE_2D;
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break;
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default:
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assert(0);
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}
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if (is_stencil)
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surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
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else
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surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
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surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
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2015-10-20 23:10:36 +01:00
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2015-10-26 10:11:44 +00:00
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if (AddrSurfInfoIn->flags.dccCompatible) {
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2015-10-20 23:10:36 +01:00
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AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
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AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
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AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
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AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
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AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
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ret = AddrComputeDccInfo(ws->addrlib,
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AddrDccIn,
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AddrDccOut);
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if (ret == ADDR_OK) {
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surf_level->dcc_offset = surf->dcc_size;
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surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
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surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
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} else {
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2015-10-26 10:11:44 +00:00
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surf->dcc_size = 0;
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2015-10-20 23:10:36 +01:00
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surf_level->dcc_offset = 0;
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}
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} else {
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2015-10-26 10:11:44 +00:00
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surf->dcc_size = 0;
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2015-10-20 23:10:36 +01:00
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surf_level->dcc_offset = 0;
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}
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2015-04-16 18:41:33 +01:00
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return 0;
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}
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static int amdgpu_surface_init(struct radeon_winsys *rws,
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struct radeon_surf *surf)
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{
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struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
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unsigned level, mode, type;
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bool compressed;
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ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
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2015-10-20 23:10:36 +01:00
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ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
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ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
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2015-04-16 18:41:33 +01:00
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ADDR_TILEINFO AddrTileInfoIn = {0};
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ADDR_TILEINFO AddrTileInfoOut = {0};
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int r;
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r = amdgpu_surface_sanity(surf);
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if (r)
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return r;
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AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
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AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
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2015-10-20 23:10:36 +01:00
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AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
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AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
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2015-04-16 18:41:33 +01:00
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AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
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type = RADEON_SURF_GET(surf->flags, TYPE);
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mode = RADEON_SURF_GET(surf->flags, MODE);
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compressed = surf->blk_w == 4 && surf->blk_h == 4;
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/* MSAA and FMASK require 2D tiling. */
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if (surf->nsamples > 1 ||
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(surf->flags & RADEON_SURF_FMASK))
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mode = RADEON_SURF_MODE_2D;
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/* DB doesn't support linear layouts. */
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if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
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mode < RADEON_SURF_MODE_1D)
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mode = RADEON_SURF_MODE_1D;
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/* Set the requested tiling mode. */
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switch (mode) {
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case RADEON_SURF_MODE_LINEAR_ALIGNED:
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AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
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break;
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case RADEON_SURF_MODE_1D:
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AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
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break;
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case RADEON_SURF_MODE_2D:
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AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
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break;
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default:
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assert(0);
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}
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/* The format must be set correctly for the allocation of compressed
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* textures to work. In other cases, setting the bpp is sufficient. */
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if (compressed) {
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switch (surf->bpe) {
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case 8:
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AddrSurfInfoIn.format = ADDR_FMT_BC1;
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break;
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case 16:
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AddrSurfInfoIn.format = ADDR_FMT_BC3;
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break;
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default:
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assert(0);
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}
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}
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else {
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2015-10-20 23:10:36 +01:00
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AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
|
2015-04-16 18:41:33 +01:00
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}
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2015-10-20 23:10:36 +01:00
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AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
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2015-04-16 18:41:33 +01:00
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AddrSurfInfoIn.tileIndex = -1;
|
|
|
|
|
|
|
|
/* Set the micro tile type. */
|
|
|
|
if (surf->flags & RADEON_SURF_SCANOUT)
|
|
|
|
AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
|
|
|
|
else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
|
|
|
|
AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
|
|
|
|
else
|
|
|
|
AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
|
|
|
|
|
|
|
|
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
|
|
|
|
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
|
|
|
|
AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
|
|
|
|
AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
|
|
|
|
AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
|
|
|
|
AddrSurfInfoIn.flags.degrade4Space = 1;
|
2015-10-26 10:11:44 +00:00
|
|
|
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
|
|
|
|
!(surf->flags & RADEON_SURF_SCANOUT) &&
|
|
|
|
!compressed && AddrDccIn.numSamples <= 1;
|
2015-04-16 18:41:33 +01:00
|
|
|
|
2016-05-19 19:10:10 +01:00
|
|
|
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
|
|
|
|
AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
|
|
|
|
|
|
|
|
/* TODO: update addrlib to a newer version, remove this, and
|
|
|
|
* set flags.matchStencilTileCfg = 1 to fix stencil texturing.
|
|
|
|
*/
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.flags.noStencil = 1;
|
|
|
|
|
|
|
|
/* Set preferred macrotile parameters. This is usually required
|
|
|
|
* for shared resources. This is for 2D tiling only. */
|
|
|
|
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
|
|
|
|
surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
|
|
|
|
/* If any of these parameters are incorrect, the calculation
|
|
|
|
* will fail. */
|
2016-05-01 12:47:47 +01:00
|
|
|
AddrTileInfoIn.banks = surf->num_banks;
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrTileInfoIn.bankWidth = surf->bankw;
|
|
|
|
AddrTileInfoIn.bankHeight = surf->bankh;
|
|
|
|
AddrTileInfoIn.macroAspectRatio = surf->mtilea;
|
|
|
|
AddrTileInfoIn.tileSplitBytes = surf->tile_split;
|
2016-05-01 12:56:01 +01:00
|
|
|
AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.flags.degrade4Space = 0;
|
|
|
|
AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
|
|
|
|
|
|
|
|
/* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
|
|
|
|
* the tile index, because we are expected to know it if
|
|
|
|
* we know the other parameters.
|
|
|
|
*
|
|
|
|
* This is something that can easily be fixed in Addrlib.
|
|
|
|
* For now, just figure it out here.
|
|
|
|
* Note that only 2D_TILE_THIN1 is handled here.
|
|
|
|
*/
|
|
|
|
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
|
|
|
|
assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
|
|
|
|
|
|
|
|
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
|
|
|
|
AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
|
|
|
|
else
|
|
|
|
AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
|
|
|
|
}
|
|
|
|
|
|
|
|
surf->bo_size = 0;
|
2015-10-20 23:10:36 +01:00
|
|
|
surf->dcc_size = 0;
|
|
|
|
surf->dcc_alignment = 1;
|
2015-04-16 18:41:33 +01:00
|
|
|
|
|
|
|
/* Calculate texture layout information. */
|
|
|
|
for (level = 0; level <= surf->last_level; level++) {
|
|
|
|
r = compute_level(ws, surf, false, level, type, compressed,
|
2015-10-20 23:10:36 +01:00
|
|
|
&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
|
2015-04-16 18:41:33 +01:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
if (level == 0) {
|
|
|
|
surf->bo_alignment = AddrSurfInfoOut.baseAlign;
|
|
|
|
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
|
|
|
|
|
|
|
|
/* For 2D modes only. */
|
|
|
|
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
|
|
|
surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
|
|
|
|
surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
|
|
|
|
surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
|
|
|
|
surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
|
|
|
surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
|
2016-04-26 17:30:07 +01:00
|
|
|
surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
|
|
|
|
} else {
|
|
|
|
surf->macro_tile_index = 0;
|
2015-04-16 18:41:33 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate texture layout information for stencil. */
|
|
|
|
if (surf->flags & RADEON_SURF_SBUFFER) {
|
|
|
|
AddrSurfInfoIn.bpp = 8;
|
2016-05-19 19:10:10 +01:00
|
|
|
AddrSurfInfoIn.flags.depth = 0;
|
|
|
|
AddrSurfInfoIn.flags.stencil = 1;
|
2015-04-16 18:41:33 +01:00
|
|
|
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
|
|
|
|
AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
|
|
|
|
|
|
|
|
for (level = 0; level <= surf->last_level; level++) {
|
|
|
|
r = compute_level(ws, surf, true, level, type, compressed,
|
2015-10-20 23:10:36 +01:00
|
|
|
&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
|
2015-04-16 18:41:33 +01:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
if (level == 0) {
|
|
|
|
surf->stencil_offset = surf->stencil_level[0].offset;
|
|
|
|
|
|
|
|
/* For 2D modes only. */
|
|
|
|
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
|
|
|
surf->stencil_tile_split =
|
|
|
|
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int amdgpu_surface_best(struct radeon_winsys *rws,
|
|
|
|
struct radeon_surf *surf)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
|
|
|
|
{
|
|
|
|
ws->base.surface_init = amdgpu_surface_init;
|
|
|
|
ws->base.surface_best = amdgpu_surface_best;
|
|
|
|
}
|