2015-04-16 21:43:23 +01:00
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/*
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* Copyright © 2011 Marek Olšák <maraeo@gmail.com>
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* Copyright © 2015 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/*
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* Authors:
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* Marek Olšák <maraeo@gmail.com>
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*/
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#ifndef AMDGPU_CS_H
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#define AMDGPU_CS_H
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#include "amdgpu_bo.h"
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#include "util/u_memory.h"
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struct amdgpu_ctx {
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struct amdgpu_winsys *ws;
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amdgpu_context_handle ctx;
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amdgpu_bo_handle user_fence_bo;
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uint64_t *user_fence_cpu_address_base;
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int refcount;
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};
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struct amdgpu_cs_buffer {
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struct amdgpu_winsys_bo *bo;
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2015-09-26 23:52:32 +01:00
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uint64_t priority_usage;
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2015-04-16 21:43:23 +01:00
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enum radeon_bo_usage usage;
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enum radeon_bo_domain domains;
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};
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2016-05-07 03:16:05 +01:00
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enum ib_type {
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IB_CONST_PREAMBLE = 0,
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IB_CONST = 1, /* the const IB must be first */
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IB_MAIN = 2,
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IB_NUM
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};
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2015-08-08 12:27:38 +01:00
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struct amdgpu_ib {
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struct radeon_winsys_cs base;
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/* A buffer out of which new IBs are allocated. */
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struct pb_buffer *big_ib_buffer;
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uint8_t *ib_mapped;
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unsigned used_ib_space;
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2016-05-07 16:58:13 +01:00
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unsigned max_ib_size;
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2016-05-07 03:33:17 +01:00
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uint32_t *ptr_ib_size;
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2016-05-07 03:16:05 +01:00
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enum ib_type ib_type;
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2015-08-08 13:02:02 +01:00
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};
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2016-03-08 00:19:31 +00:00
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struct amdgpu_cs_context {
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2015-04-16 21:43:23 +01:00
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struct amdgpu_cs_request request;
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2015-08-08 13:02:02 +01:00
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struct amdgpu_cs_ib_info ib[IB_NUM];
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2015-04-16 21:43:23 +01:00
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2015-09-26 23:10:00 +01:00
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/* Buffers. */
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2015-04-16 21:43:23 +01:00
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unsigned max_num_buffers;
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unsigned num_buffers;
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amdgpu_bo_handle *handles;
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uint8_t *flags;
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struct amdgpu_cs_buffer *buffers;
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2016-03-08 15:01:47 +00:00
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int buffer_indices_hashlist[4096];
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2015-04-16 21:43:23 +01:00
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2015-08-17 18:55:57 +01:00
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uint64_t used_vram;
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uint64_t used_gart;
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2015-04-16 21:43:23 +01:00
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unsigned max_dependencies;
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2016-03-08 00:19:31 +00:00
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struct pipe_fence_handle *fence;
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};
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struct amdgpu_cs {
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struct amdgpu_ib main; /* must be first because this is inherited */
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struct amdgpu_ib const_ib; /* optional constant engine IB */
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struct amdgpu_ib const_preamble_ib;
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struct amdgpu_ctx *ctx;
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enum ring_type ring_type;
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/* We flip between these two CS. While one is being consumed
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* by the kernel in another thread, the other one is being filled
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* by the pipe driver. */
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struct amdgpu_cs_context csc1;
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struct amdgpu_cs_context csc2;
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/* The currently-used CS. */
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struct amdgpu_cs_context *csc;
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/* The CS being currently-owned by the other thread. */
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struct amdgpu_cs_context *cst;
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/* Flush CS. */
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void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);
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void *flush_data;
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2016-06-11 12:10:49 +01:00
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struct util_queue_fence flush_completed;
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2015-04-16 21:43:23 +01:00
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};
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struct amdgpu_fence {
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struct pipe_reference reference;
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struct amdgpu_ctx *ctx; /* submission context */
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struct amdgpu_cs_fence fence;
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uint64_t *user_fence_cpu_address;
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2016-03-08 00:19:31 +00:00
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/* If the fence is unknown due to an IB still being submitted
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* in the other thread. */
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volatile int submission_in_progress; /* bool (int for atomicity) */
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2015-04-16 21:43:23 +01:00
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volatile int signalled; /* bool (int for atomicity) */
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};
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static inline void amdgpu_ctx_unref(struct amdgpu_ctx *ctx)
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{
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if (p_atomic_dec_zero(&ctx->refcount)) {
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amdgpu_cs_ctx_free(ctx->ctx);
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amdgpu_bo_free(ctx->user_fence_bo);
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FREE(ctx);
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}
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}
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static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
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struct pipe_fence_handle *src)
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{
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struct amdgpu_fence **rdst = (struct amdgpu_fence **)dst;
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struct amdgpu_fence *rsrc = (struct amdgpu_fence *)src;
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if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
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amdgpu_ctx_unref((*rdst)->ctx);
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FREE(*rdst);
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}
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*rdst = rsrc;
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}
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2016-03-08 00:19:31 +00:00
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int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo);
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2015-04-16 21:43:23 +01:00
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2016-05-07 03:16:05 +01:00
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static inline struct amdgpu_ib *
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amdgpu_ib(struct radeon_winsys_cs *base)
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{
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return (struct amdgpu_ib *)base;
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}
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2015-04-16 21:43:23 +01:00
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static inline struct amdgpu_cs *
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amdgpu_cs(struct radeon_winsys_cs *base)
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{
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2016-05-07 03:16:05 +01:00
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assert(amdgpu_ib(base)->ib_type == IB_MAIN);
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2015-04-16 21:43:23 +01:00
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return (struct amdgpu_cs*)base;
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}
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2016-05-07 03:16:05 +01:00
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#define get_container(member_ptr, container_type, container_member) \
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(container_type *)((char *)(member_ptr) - offsetof(container_type, container_member))
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static inline struct amdgpu_cs *
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amdgpu_cs_from_ib(struct amdgpu_ib *ib)
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{
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switch (ib->ib_type) {
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case IB_MAIN:
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return get_container(ib, struct amdgpu_cs, main);
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case IB_CONST:
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return get_container(ib, struct amdgpu_cs, const_ib);
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case IB_CONST_PREAMBLE:
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return get_container(ib, struct amdgpu_cs, const_preamble_ib);
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default:
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unreachable("bad ib_type");
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}
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}
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2016-06-21 20:29:39 +01:00
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static inline bool
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2015-04-16 21:43:23 +01:00
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amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
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struct amdgpu_winsys_bo *bo)
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{
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int num_refs = bo->num_cs_references;
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2015-12-06 21:19:38 +00:00
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return num_refs == bo->ws->num_cs ||
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2016-03-08 00:19:31 +00:00
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(num_refs && amdgpu_lookup_buffer(cs->csc, bo) != -1);
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2015-04-16 21:43:23 +01:00
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}
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2016-06-21 20:29:39 +01:00
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static inline bool
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2015-04-16 21:43:23 +01:00
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amdgpu_bo_is_referenced_by_cs_with_usage(struct amdgpu_cs *cs,
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struct amdgpu_winsys_bo *bo,
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enum radeon_bo_usage usage)
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{
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int index;
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if (!bo->num_cs_references)
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2016-06-21 20:29:39 +01:00
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return false;
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2015-04-16 21:43:23 +01:00
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2016-03-08 00:19:31 +00:00
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index = amdgpu_lookup_buffer(cs->csc, bo);
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2015-04-16 21:43:23 +01:00
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if (index == -1)
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2016-06-21 20:29:39 +01:00
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return false;
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2015-04-16 21:43:23 +01:00
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2016-03-08 00:19:31 +00:00
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return (cs->csc->buffers[index].usage & usage) != 0;
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2015-04-16 21:43:23 +01:00
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}
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2016-06-21 20:29:39 +01:00
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static inline bool
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2015-04-16 21:43:23 +01:00
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amdgpu_bo_is_referenced_by_any_cs(struct amdgpu_winsys_bo *bo)
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{
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return bo->num_cs_references != 0;
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}
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bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
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bool absolute);
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2016-03-08 00:19:31 +00:00
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void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs);
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2015-04-16 21:43:23 +01:00
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void amdgpu_cs_init_functions(struct amdgpu_winsys *ws);
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2016-06-11 14:40:28 +01:00
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void amdgpu_cs_submit_ib(void *job, int thread_index);
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2015-04-16 21:43:23 +01:00
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#endif
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