609 lines
20 KiB
C
609 lines
20 KiB
C
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/*
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* Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "pipe/p_state.h"
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#include "util/u_string.h"
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#include "util/u_memory.h"
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#include "util/u_inlines.h"
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#include "util/u_format.h"
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#include "util/bitset.h"
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#include "freedreno_program.h"
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#include "fd5_program.h"
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#include "fd5_emit.h"
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#include "fd5_texture.h"
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#include "fd5_format.h"
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static void
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delete_shader_stateobj(struct fd5_shader_stateobj *so)
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{
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ir3_shader_destroy(so->shader);
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free(so);
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}
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static struct fd5_shader_stateobj *
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create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
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enum shader_t type)
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{
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struct fd_context *ctx = fd_context(pctx);
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struct ir3_compiler *compiler = ctx->screen->compiler;
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struct fd5_shader_stateobj *so = CALLOC_STRUCT(fd5_shader_stateobj);
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so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
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return so;
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}
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static void *
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fd5_fp_state_create(struct pipe_context *pctx,
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const struct pipe_shader_state *cso)
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{
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return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
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}
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static void
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fd5_fp_state_delete(struct pipe_context *pctx, void *hwcso)
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{
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struct fd5_shader_stateobj *so = hwcso;
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delete_shader_stateobj(so);
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}
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static void *
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fd5_vp_state_create(struct pipe_context *pctx,
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const struct pipe_shader_state *cso)
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{
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return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
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}
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static void
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fd5_vp_state_delete(struct pipe_context *pctx, void *hwcso)
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{
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struct fd5_shader_stateobj *so = hwcso;
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delete_shader_stateobj(so);
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}
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static void
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emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
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{
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const struct ir3_info *si = &so->info;
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enum adreno_state_block sb;
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enum adreno_state_src src;
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uint32_t i, sz, *bin;
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if (so->type == SHADER_VERTEX) {
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sb = SB_VERT_SHADER;
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} else {
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sb = SB_FRAG_SHADER;
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}
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if (fd_mesa_debug & FD_DBG_DIRECT) {
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sz = si->sizedwords;
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src = SS_DIRECT;
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bin = fd_bo_map(so->bo);
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} else {
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sz = 0;
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src = 2; // enums different on a5xx..
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bin = NULL;
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}
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OUT_PKT7(ring, CP_LOAD_STATE, 3 + sz);
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OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
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CP_LOAD_STATE_0_STATE_SRC(src) |
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CP_LOAD_STATE_0_STATE_BLOCK(sb) |
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CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
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if (bin) {
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OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
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CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
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OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
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} else {
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OUT_RELOC(ring, so->bo, 0,
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CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
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}
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/* for how clever coverity is, it is sometimes rather dull, and
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* doesn't realize that the only case where bin==NULL, sz==0:
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*/
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assume(bin || (sz == 0));
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for (i = 0; i < sz; i++) {
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OUT_RING(ring, bin[i]);
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}
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}
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struct stage {
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const struct ir3_shader_variant *v;
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const struct ir3_info *i;
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/* const sizes are in units of 4 * vec4 */
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uint8_t constoff;
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uint8_t constlen;
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/* instr sizes are in units of 16 instructions */
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uint8_t instroff;
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uint8_t instrlen;
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};
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enum {
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VS = 0,
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FS = 1,
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HS = 2,
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DS = 3,
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GS = 4,
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MAX_STAGES
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};
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static void
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setup_stages(struct fd5_emit *emit, struct stage *s)
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{
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unsigned i;
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s[VS].v = fd5_emit_get_vp(emit);
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s[FS].v = fd5_emit_get_fp(emit);
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s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
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for (i = 0; i < MAX_STAGES; i++) {
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if (s[i].v) {
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s[i].i = &s[i].v->info;
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/* constlen is in units of 4 * vec4: */
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s[i].constlen = align(s[i].v->constlen, 4) / 4;
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/* instrlen is already in units of 16 instr.. although
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* probably we should ditch that and not make the compiler
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* care about instruction group size of a3xx vs a5xx
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*/
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s[i].instrlen = s[i].v->instrlen;
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} else {
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s[i].i = NULL;
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s[i].constlen = 0;
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s[i].instrlen = 0;
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}
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}
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/* NOTE: at least for gles2, blob partitions VS at bottom of const
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* space and FS taking entire remaining space. We probably don't
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* need to do that the same way, but for now mimic what the blob
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* does to make it easier to diff against register values from blob
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*
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* NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
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* is run from external memory.
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*/
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if ((s[VS].instrlen + s[FS].instrlen) > 64) {
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/* prioritize FS for internal memory: */
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if (s[FS].instrlen < 64) {
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/* if FS can fit, kick VS out to external memory: */
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s[VS].instrlen = 0;
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} else if (s[VS].instrlen < 64) {
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/* otherwise if VS can fit, kick out FS: */
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s[FS].instrlen = 0;
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} else {
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/* neither can fit, run both from external memory: */
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s[VS].instrlen = 0;
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s[FS].instrlen = 0;
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}
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}
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unsigned constoff = 0;
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for (i = 0; i < MAX_STAGES; i++) {
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s[i].constoff = constoff;
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constoff += s[i].constlen;
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}
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s[VS].instroff = 0;
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s[FS].instroff = 64 - s[FS].instrlen;
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s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
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}
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void
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fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit,
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int nr, struct pipe_surface **bufs)
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{
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struct stage s[MAX_STAGES];
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uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
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uint32_t face_regid, coord_regid, zwcoord_regid;
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uint32_t vcoord_regid, vertex_regid, instance_regid;
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int i, j;
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debug_assert(nr <= ARRAY_SIZE(color_regid));
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if (emit->key.binning_pass)
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nr = 0;
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setup_stages(emit, s);
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pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
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posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
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psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
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vertex_regid = ir3_find_output_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
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instance_regid = ir3_find_output_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
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if (s[FS].v->color0_mrt) {
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color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
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color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
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ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
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} else {
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color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
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color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
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color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
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color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
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color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
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color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
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color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
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color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
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}
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/* TODO get these dynamically: */
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face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
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coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
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zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
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vcoord_regid = (s[FS].v->total_in > 0) ? regid(0,0) : regid(63,0);
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/* we could probably divide this up into things that need to be
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* emitted if frag-prog is dirty vs if vert-prog is dirty..
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*/
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OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONTROL_REG, 5);
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OUT_RING(ring, A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
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A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff) |
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COND(s[VS].v, A5XX_HLSQ_VS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
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A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff) |
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COND(s[FS].v, A5XX_HLSQ_FS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
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A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff) |
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COND(s[HS].v, A5XX_HLSQ_HS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
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A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff) |
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COND(s[DS].v, A5XX_HLSQ_DS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
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A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff) |
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COND(s[GS].v, A5XX_HLSQ_GS_CONTROL_REG_ENABLED));
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OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
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OUT_RING(ring, 0x00000000);
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OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
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OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen));
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OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen));
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OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen));
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OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen));
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OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen));
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OUT_PKT4(ring, REG_A5XX_SP_VS_CONTROL_REG, 5);
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OUT_RING(ring, A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
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A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff) |
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COND(s[VS].v, A5XX_SP_VS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
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A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff) |
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COND(s[FS].v, A5XX_SP_FS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
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A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff) |
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COND(s[HS].v, A5XX_SP_HS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
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A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff) |
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COND(s[DS].v, A5XX_SP_DS_CONTROL_REG_ENABLED));
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OUT_RING(ring, A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
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A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff) |
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COND(s[GS].v, A5XX_SP_GS_CONTROL_REG_ENABLED));
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OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
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OUT_RING(ring, 0x00000000);
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OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
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OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
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OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
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OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
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OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
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OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
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OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
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OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
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OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
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OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
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OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
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OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
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OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
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OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
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OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
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OUT_PKT4(ring, REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3, 2);
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OUT_RING(ring, 0x00000000); /* HLSQ_CONTEXT_SWITCH_CS_SW_3 */
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OUT_RING(ring, 0x00000000); /* HLSQ_CONTEXT_SWITCH_CS_SW_4 */
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OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
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OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
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A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
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0x6 | /* XXX seems to be always set? */
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A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
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COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
|
||
|
|
||
|
struct ir3_shader_linkage l = {0};
|
||
|
ir3_link_shaders(&l, s[VS].v, s[FS].v);
|
||
|
|
||
|
/* a5xx appends pos/psize to end of the linkage map: */
|
||
|
if (pos_regid != regid(63,0))
|
||
|
ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
|
||
|
|
||
|
if (psize_regid != regid(63,0))
|
||
|
ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
|
||
|
|
||
|
for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
|
||
|
uint32_t reg = 0;
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
|
||
|
|
||
|
reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
|
||
|
reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
|
||
|
j++;
|
||
|
|
||
|
reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
|
||
|
reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
|
||
|
j++;
|
||
|
|
||
|
OUT_RING(ring, reg);
|
||
|
}
|
||
|
|
||
|
for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
|
||
|
uint32_t reg = 0;
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
|
||
|
|
||
|
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
|
||
|
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
|
||
|
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
|
||
|
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
|
||
|
|
||
|
OUT_RING(ring, reg);
|
||
|
}
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
|
||
|
OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
|
||
|
|
||
|
if (s[VS].instrlen)
|
||
|
emit_shader(ring, s[VS].v);
|
||
|
|
||
|
BITSET_DECLARE(varbs, 128) = {0};
|
||
|
uint32_t *varmask = (uint32_t *)varbs;
|
||
|
|
||
|
for (i = 0; i < l.cnt; i++)
|
||
|
for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
|
||
|
BITSET_SET(varbs, l.var[i].loc + j);
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
|
||
|
OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
|
||
|
OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
|
||
|
OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
|
||
|
OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
|
||
|
|
||
|
// TODO depending on other bits in this reg (if any) set somewhere else?
|
||
|
OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
|
||
|
OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
|
||
|
|
||
|
if (emit->key.binning_pass) {
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
|
||
|
OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
|
||
|
OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
|
||
|
} else {
|
||
|
uint32_t stride_in_vpc = align(s[FS].v->total_in, 4) + 4;
|
||
|
|
||
|
if (s[VS].v->writes_psize)
|
||
|
stride_in_vpc++;
|
||
|
|
||
|
// TODO if some of these other bits depend on something other than
|
||
|
// program state we should probably move these next three regs:
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
|
||
|
OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
|
||
|
OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(stride_in_vpc) |
|
||
|
COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
|
||
|
0x10000); // XXX
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
|
||
|
OUT_RING(ring, A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(stride_in_vpc) |
|
||
|
0x400); // XXX
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
|
||
|
OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
|
||
|
}
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
|
||
|
OUT_RING(ring, 0x00000881); /* XXX HLSQ_CONTROL_0 */
|
||
|
OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
|
||
|
OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
|
||
|
0xfcfcfc00); /* XXX */
|
||
|
OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
|
||
|
0xfcfcfc00); /* XXX */
|
||
|
OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
|
||
|
A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
|
||
|
0x0000fcfc); /* XXX */
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
|
||
|
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING));
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
|
||
|
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
|
||
|
0x4000e | /* XXX set pretty much everywhere */
|
||
|
A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
|
||
|
A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
|
||
|
A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
|
||
|
COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
|
||
|
OUT_RING(ring, 0x020fffff); /* XXX */
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
|
||
|
OUT_RING(ring, 0x0000ffff); /* XXX */
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
|
||
|
OUT_RING(ring, 0x00000010); /* XXX */
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 3);
|
||
|
OUT_RING(ring,
|
||
|
COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
|
||
|
COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
|
||
|
A5XX_RB_RENDER_CONTROL0_YCOORD |
|
||
|
A5XX_RB_RENDER_CONTROL0_ZCOORD |
|
||
|
A5XX_RB_RENDER_CONTROL0_WCOORD));
|
||
|
OUT_RING(ring,
|
||
|
COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS));
|
||
|
OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
|
||
|
COND(s[FS].v->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 9);
|
||
|
OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
|
||
|
A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
|
||
|
A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
|
||
|
for (i = 0; i < 8; i++) {
|
||
|
OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
|
||
|
COND(emit->key.half_precision,
|
||
|
A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
|
||
|
}
|
||
|
|
||
|
if (emit->key.binning_pass) {
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
|
||
|
OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(0));
|
||
|
} else {
|
||
|
uint32_t vinterp[8], vpsrepl[8];
|
||
|
|
||
|
memset(vinterp, 0, sizeof(vinterp));
|
||
|
memset(vpsrepl, 0, sizeof(vpsrepl));
|
||
|
|
||
|
/* looks like we need to do int varyings in the frag
|
||
|
* shader on a5xx (no flatshad reg? or a420.0 bug?):
|
||
|
*
|
||
|
* (sy)(ss)nop
|
||
|
* (sy)ldlv.u32 r0.x,l[r0.x], 1
|
||
|
* ldlv.u32 r0.y,l[r0.x+1], 1
|
||
|
* (ss)bary.f (ei)r63.x, 0, r0.x
|
||
|
* (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
|
||
|
* (rpt5)nop
|
||
|
* sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
|
||
|
*
|
||
|
* Possibly on later a5xx variants we'll be able to use
|
||
|
* something like the code below instead of workaround
|
||
|
* in the shader:
|
||
|
*/
|
||
|
/* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
|
||
|
for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
|
||
|
/* NOTE: varyings are packed, so if compmask is 0xb
|
||
|
* then first, third, and fourth component occupy
|
||
|
* three consecutive varying slots:
|
||
|
*/
|
||
|
unsigned compmask = s[FS].v->inputs[j].compmask;
|
||
|
|
||
|
uint32_t inloc = s[FS].v->inputs[j].inloc;
|
||
|
|
||
|
if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
|
||
|
(s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
|
||
|
uint32_t loc = inloc;
|
||
|
|
||
|
for (i = 0; i < 4; i++) {
|
||
|
if (compmask & (1 << i)) {
|
||
|
vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
|
||
|
//flatshade[loc / 32] |= 1 << (loc % 32);
|
||
|
loc++;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
gl_varying_slot slot = s[FS].v->inputs[j].slot;
|
||
|
|
||
|
/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
|
||
|
if (slot >= VARYING_SLOT_VAR0) {
|
||
|
unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
|
||
|
/* Replace the .xy coordinates with S/T from the point sprite. Set
|
||
|
* interpolation bits for .zw such that they become .01
|
||
|
*/
|
||
|
if (emit->sprite_coord_enable & texmask) {
|
||
|
/* mask is two 2-bit fields, where:
|
||
|
* '01' -> S
|
||
|
* '10' -> T
|
||
|
* '11' -> 1 - T (flip mode)
|
||
|
*/
|
||
|
unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
|
||
|
uint32_t loc = inloc;
|
||
|
if (compmask & 0x1) {
|
||
|
vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
|
||
|
loc++;
|
||
|
}
|
||
|
if (compmask & 0x2) {
|
||
|
vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
|
||
|
loc++;
|
||
|
}
|
||
|
if (compmask & 0x4) {
|
||
|
/* .z <- 0.0f */
|
||
|
vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
|
||
|
loc++;
|
||
|
}
|
||
|
if (compmask & 0x8) {
|
||
|
/* .w <- 1.0f */
|
||
|
vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
|
||
|
loc++;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
|
||
|
OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
|
||
|
(s[VS].v->writes_psize ? 0x0c00 : 0xff00)); // XXX
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
|
||
|
for (i = 0; i < 8; i++)
|
||
|
OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
|
||
|
for (i = 0; i < 8; i++)
|
||
|
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
|
||
|
}
|
||
|
|
||
|
if (!emit->key.binning_pass)
|
||
|
if (s[FS].instrlen)
|
||
|
emit_shader(ring, s[FS].v);
|
||
|
|
||
|
OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
|
||
|
OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
|
||
|
A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
|
||
|
0xfc);
|
||
|
OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
|
||
|
OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
|
||
|
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
|
||
|
OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
|
||
|
}
|
||
|
|
||
|
void
|
||
|
fd5_prog_init(struct pipe_context *pctx)
|
||
|
{
|
||
|
pctx->create_fs_state = fd5_fp_state_create;
|
||
|
pctx->delete_fs_state = fd5_fp_state_delete;
|
||
|
|
||
|
pctx->create_vs_state = fd5_vp_state_create;
|
||
|
pctx->delete_vs_state = fd5_vp_state_delete;
|
||
|
|
||
|
fd_prog_init(pctx);
|
||
|
}
|