2021-03-19 19:52:44 +00:00
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/*
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* Copyright © 2021 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/* Make the test not meaningless when asserts are disabled. */
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#undef NDEBUG
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#include <assert.h>
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <amdgpu.h>
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#include "drm-uapi/amdgpu_drm.h"
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#include "drm-uapi/drm_fourcc.h"
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#include "ac_surface.h"
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#include "util/macros.h"
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#include "util/u_atomic.h"
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#include "util/u_math.h"
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#include "util/u_vector.h"
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#include "util/mesa-sha1.h"
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#include "addrlib/inc/addrinterface.h"
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#include "ac_surface_test_common.h"
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/*
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2021-04-06 09:48:41 +01:00
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* The main goal of this test is to validate that our dcc/htile addressing
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* functions match addrlib behavior.
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2021-03-19 19:52:44 +00:00
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*/
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2021-07-30 12:41:53 +01:00
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/* DCC address computation without mipmapping.
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* CMASK address computation without mipmapping and without multisampling.
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*/
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static unsigned gfx9_meta_addr_from_coord(const struct radeon_info *info,
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/* Shader key inputs: */
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/* equation varies with resource_type, swizzle_mode,
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* bpp, number of fragments, pipe_aligned, rb_aligned */
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const struct gfx9_addr_meta_equation *eq,
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unsigned meta_block_width, unsigned meta_block_height,
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unsigned meta_block_depth,
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/* Shader inputs: */
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unsigned meta_pitch, unsigned meta_height,
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unsigned x, unsigned y, unsigned z,
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unsigned sample, unsigned pipe_xor,
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/* Shader outputs (CMASK only): */
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unsigned *bit_position)
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2021-03-19 19:52:44 +00:00
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{
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/* The compiled shader shouldn't be complicated considering there are a lot of constants here. */
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unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
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unsigned meta_block_depth_log2 = util_logbase2(meta_block_depth);
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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2021-07-30 12:58:25 +01:00
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unsigned numPipeBits = eq->numPipeBits;
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2021-07-30 12:41:53 +01:00
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unsigned pitchInBlock = meta_pitch >> meta_block_width_log2;
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unsigned sliceSizeInBlock = (meta_height >> meta_block_height_log2) * pitchInBlock;
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2021-03-19 19:52:44 +00:00
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unsigned xb = x >> meta_block_width_log2;
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unsigned yb = y >> meta_block_height_log2;
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unsigned zb = z >> meta_block_depth_log2;
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unsigned blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
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unsigned coords[] = {x, y, z, sample, blockIndex};
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unsigned address = 0;
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2021-07-30 12:58:25 +01:00
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unsigned num_bits = eq->num_bits;
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2021-03-19 19:52:44 +00:00
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assert(num_bits <= 32);
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/* Compute the address up until the last bit that doesn't use the block index. */
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for (unsigned b = 0; b < num_bits - 1; b++) {
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unsigned xor = 0;
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for (unsigned c = 0; c < 5; c++) {
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2021-07-30 12:58:25 +01:00
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if (eq->bit[b].coord[c].dim >= 5)
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2021-03-19 19:52:44 +00:00
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continue;
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2021-07-30 12:58:25 +01:00
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assert(eq->bit[b].coord[c].ord < 32);
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unsigned ison = (coords[eq->bit[b].coord[c].dim] >>
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eq->bit[b].coord[c].ord) & 0x1;
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2021-03-19 19:52:44 +00:00
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xor ^= ison;
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}
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address |= xor << b;
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}
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/* Fill the remaining bits with the block index. */
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unsigned last = num_bits - 1;
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2021-07-30 12:58:25 +01:00
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address |= (blockIndex >> eq->bit[last].coord[0].ord) << last;
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2021-03-19 19:52:44 +00:00
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2021-07-30 12:41:53 +01:00
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if (bit_position)
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*bit_position = (address & 1) << 2;
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2021-03-19 19:52:44 +00:00
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unsigned pipeXor = pipe_xor & ((1 << numPipeBits) - 1);
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return (address >> 1) ^ (pipeXor << m_pipeInterleaveLog2);
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}
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2021-08-03 12:29:52 +01:00
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/* DCC/CMASK/HTILE address computation for GFX10. */
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2021-04-06 09:48:41 +01:00
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static unsigned gfx10_meta_addr_from_coord(const struct radeon_info *info,
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/* Shader key inputs: */
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const uint16_t *equation,
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unsigned meta_block_width, unsigned meta_block_height,
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unsigned blkSizeLog2,
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/* Shader inputs: */
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unsigned meta_pitch, unsigned meta_slice_size,
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unsigned x, unsigned y, unsigned z,
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2021-08-03 12:29:52 +01:00
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unsigned pipe_xor,
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/* Shader outputs: (CMASK only) */
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unsigned *bit_position)
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2021-03-19 19:52:44 +00:00
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{
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/* The compiled shader shouldn't be complicated considering there are a lot of constants here. */
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unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
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unsigned coord[] = {x, y, z, 0};
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unsigned address = 0;
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for (unsigned i = 0; i < blkSizeLog2 + 1; i++) {
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unsigned v = 0;
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for (unsigned c = 0; c < 4; c++) {
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if (equation[i*4+c] != 0) {
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unsigned mask = equation[i*4+c];
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unsigned bits = coord[c];
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while (mask)
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v ^= (bits >> u_bit_scan(&mask)) & 0x1;
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}
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}
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address |= v << i;
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}
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unsigned blkMask = (1 << blkSizeLog2) - 1;
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unsigned pipeMask = (1 << G_0098F8_NUM_PIPES(info->gb_addr_config)) - 1;
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unsigned m_pipeInterleaveLog2 = 8 + G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config);
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unsigned xb = x >> meta_block_width_log2;
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unsigned yb = y >> meta_block_height_log2;
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2021-04-06 09:48:41 +01:00
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unsigned pb = meta_pitch >> meta_block_width_log2;
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2021-03-19 19:52:44 +00:00
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unsigned blkIndex = (yb * pb) + xb;
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unsigned pipeXor = ((pipe_xor & pipeMask) << m_pipeInterleaveLog2) & blkMask;
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2021-08-03 12:29:52 +01:00
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if (bit_position)
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*bit_position = (address & 1) << 2;
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2021-04-06 09:48:41 +01:00
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return (meta_slice_size * z) +
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2021-03-19 19:52:44 +00:00
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(blkIndex * (1 << blkSizeLog2)) +
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((address >> 1) ^ pipeXor);
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}
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2021-04-06 09:48:41 +01:00
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/* DCC address computation without mipmapping and MSAA. */
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static unsigned gfx10_dcc_addr_from_coord(const struct radeon_info *info,
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/* Shader key inputs: */
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/* equation varies with bpp and pipe_aligned */
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const uint16_t *equation, unsigned bpp,
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unsigned meta_block_width, unsigned meta_block_height,
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/* Shader inputs: */
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unsigned dcc_pitch, unsigned dcc_slice_size,
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unsigned x, unsigned y, unsigned z,
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unsigned pipe_xor)
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{
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unsigned bpp_log2 = util_logbase2(bpp >> 3);
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unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
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unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
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unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 + bpp_log2 - 8;
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return gfx10_meta_addr_from_coord(info, equation,
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meta_block_width, meta_block_height,
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blkSizeLog2,
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dcc_pitch, dcc_slice_size,
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2021-08-03 12:29:52 +01:00
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x, y, z, pipe_xor, NULL);
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2021-04-06 09:48:41 +01:00
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}
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2021-03-19 19:52:44 +00:00
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static bool one_dcc_address_test(const char *name, const char *test, ADDR_HANDLE addrlib,
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const struct radeon_info *info, unsigned width, unsigned height,
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unsigned depth, unsigned samples, unsigned bpp,
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unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned,
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unsigned mrt_index,
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unsigned start_x, unsigned start_y, unsigned start_z,
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unsigned start_sample)
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{
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ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT)};
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ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT)};
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ADDR2_COMPUTE_DCCINFO_INPUT din = {sizeof(din)};
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ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {sizeof(dout)};
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT in = {sizeof(in)};
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ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT out = {sizeof(out)};
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ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0};
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dout.pMipInfo = meta_mip_info;
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/* Compute DCC info. */
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in.dccKeyFlags.pipeAligned = din.dccKeyFlags.pipeAligned = pipe_aligned;
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in.dccKeyFlags.rbAligned = din.dccKeyFlags.rbAligned = rb_aligned;
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xin.resourceType = in.resourceType = din.resourceType = ADDR_RSRC_TEX_2D;
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xin.swizzleMode = in.swizzleMode = din.swizzleMode = swizzle_mode;
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in.bpp = din.bpp = bpp;
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xin.numFrags = xin.numSamples = in.numFrags = din.numFrags = samples;
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in.numMipLevels = din.numMipLevels = 1; /* addrlib can't do DccAddrFromCoord with mipmapping */
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din.unalignedWidth = width;
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din.unalignedHeight = height;
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din.numSlices = depth;
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din.firstMipIdInTail = 1;
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int ret = Addr2ComputeDccInfo(addrlib, &din, &dout);
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assert(ret == ADDR_OK);
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/* Compute xor. */
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static AddrFormat format[] = {
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ADDR_FMT_8,
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ADDR_FMT_16,
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ADDR_FMT_32,
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ADDR_FMT_32_32,
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ADDR_FMT_32_32_32_32,
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};
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xin.flags.color = 1;
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xin.flags.texture = 1;
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xin.flags.opt4space = 1;
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xin.flags.metaRbUnaligned = !rb_aligned;
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xin.flags.metaPipeUnaligned = !pipe_aligned;
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xin.format = format[util_logbase2(bpp / 8)];
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xin.surfIndex = mrt_index;
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ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
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assert(ret == ADDR_OK);
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/* Compute addresses */
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in.compressBlkWidth = dout.compressBlkWidth;
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in.compressBlkHeight = dout.compressBlkHeight;
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in.compressBlkDepth = dout.compressBlkDepth;
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in.metaBlkWidth = dout.metaBlkWidth;
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in.metaBlkHeight = dout.metaBlkHeight;
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in.metaBlkDepth = dout.metaBlkDepth;
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in.dccRamSliceSize = dout.dccRamSliceSize;
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in.mipId = 0;
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in.pitch = dout.pitch;
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in.height = dout.height;
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in.pipeXor = xout.pipeBankXor;
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2021-04-13 12:32:44 +01:00
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/* Validate that the packed gfx9_meta_equation structure can fit all fields. */
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const struct gfx9_meta_equation eq;
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2021-03-22 23:43:53 +00:00
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if (info->chip_class == GFX9) {
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2021-04-13 12:32:44 +01:00
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/* The bit array is smaller in gfx9_meta_equation than in addrlib. */
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2021-03-22 23:43:53 +00:00
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assert(dout.equation.gfx9.num_bits <= ARRAY_SIZE(eq.u.gfx9.bit));
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} else {
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2021-04-13 12:32:44 +01:00
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/* gfx9_meta_equation doesn't store the first 4 and the last 8 elements. They must be 0. */
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2021-03-22 23:43:53 +00:00
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for (unsigned i = 0; i < 4; i++)
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assert(dout.equation.gfx10_bits[i] == 0);
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for (unsigned i = ARRAY_SIZE(eq.u.gfx10_bits) + 4; i < 68; i++)
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assert(dout.equation.gfx10_bits[i] == 0);
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}
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2021-03-19 19:52:44 +00:00
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for (in.x = start_x; in.x < in.pitch; in.x += dout.compressBlkWidth) {
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for (in.y = start_y; in.y < in.height; in.y += dout.compressBlkHeight) {
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for (in.slice = start_z; in.slice < depth; in.slice += dout.compressBlkDepth) {
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for (in.sample = start_sample; in.sample < samples; in.sample++) {
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int r = Addr2ComputeDccAddrFromCoord(addrlib, &in, &out);
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if (r != ADDR_OK) {
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printf("%s addrlib error: %s\n", name, test);
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abort();
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}
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unsigned addr;
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if (info->chip_class == GFX9) {
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2021-07-30 12:41:53 +01:00
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addr = gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight,
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dout.metaBlkDepth, dout.pitch, dout.height,
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in.x, in.y, in.slice, in.sample, in.pipeXor, NULL);
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2021-04-04 21:58:29 +01:00
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if (in.sample == 1) {
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/* Sample 0 should be one byte before sample 1. The DCC MSAA clear relies on it. */
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assert(addr - 1 ==
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2021-07-30 12:41:53 +01:00
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gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight,
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dout.metaBlkDepth, dout.pitch, dout.height,
|
|
|
|
in.x, in.y, in.slice, 0, in.pipeXor, NULL));
|
2021-04-04 21:58:29 +01:00
|
|
|
}
|
2021-03-19 19:52:44 +00:00
|
|
|
} else {
|
|
|
|
addr = gfx10_dcc_addr_from_coord(info, dout.equation.gfx10_bits,
|
|
|
|
in.bpp, dout.metaBlkWidth, dout.metaBlkHeight,
|
|
|
|
dout.pitch, dout.dccRamSliceSize,
|
|
|
|
in.x, in.y, in.slice, in.pipeXor);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (out.addr != addr) {
|
|
|
|
printf("%s fail (%s) at %ux%ux%u@%u: expected = %llu, got = %u\n",
|
|
|
|
name, test, in.x, in.y, in.slice, in.sample, out.addr, addr);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void run_dcc_address_test(const char *name, const struct radeon_info *info, bool full)
|
|
|
|
{
|
|
|
|
unsigned total = 0;
|
|
|
|
unsigned fails = 0;
|
|
|
|
unsigned last_size, max_samples, min_bpp, max_bpp;
|
2021-05-07 01:41:47 +01:00
|
|
|
unsigned swizzle_modes[2], num_swizzle_modes = 0;
|
|
|
|
|
|
|
|
switch (info->chip_class) {
|
|
|
|
case GFX9:
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_S_X;
|
|
|
|
break;
|
|
|
|
case GFX10:
|
|
|
|
case GFX10_3:
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_R_X;
|
|
|
|
break;
|
|
|
|
case GFX11:
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_R_X;
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_256KB_R_X;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("unhandled gfx version");
|
|
|
|
}
|
2021-03-19 19:52:44 +00:00
|
|
|
|
|
|
|
if (full) {
|
|
|
|
last_size = 6*6 - 1;
|
|
|
|
max_samples = 8;
|
|
|
|
min_bpp = 8;
|
|
|
|
max_bpp = 128;
|
|
|
|
} else {
|
|
|
|
/* The test coverage is reduced for Gitlab CI because it timeouts. */
|
|
|
|
last_size = 0;
|
|
|
|
max_samples = 2;
|
|
|
|
min_bpp = 32;
|
|
|
|
max_bpp = 64;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef HAVE_OPENMP
|
|
|
|
#pragma omp parallel for
|
|
|
|
#endif
|
|
|
|
for (unsigned size = 0; size <= last_size; size++) {
|
|
|
|
unsigned width = 8 + 379 * (size % 6);
|
|
|
|
unsigned height = 8 + 379 * ((size / 6) % 6);
|
|
|
|
|
|
|
|
struct ac_addrlib *ac_addrlib = ac_addrlib_create(info, NULL);
|
|
|
|
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
|
|
|
|
|
|
|
|
unsigned local_fails = 0;
|
|
|
|
unsigned local_total = 0;
|
|
|
|
|
2021-05-07 01:41:47 +01:00
|
|
|
for (unsigned swizzle_mode = 0; swizzle_mode < num_swizzle_modes; swizzle_mode++) {
|
|
|
|
for (unsigned bpp = min_bpp; bpp <= max_bpp; bpp *= 2) {
|
|
|
|
/* addrlib can do DccAddrFromCoord with MSAA images only on gfx9 */
|
|
|
|
for (unsigned samples = 1; samples <= (info->chip_class == GFX9 ? max_samples : 1); samples *= 2) {
|
|
|
|
for (int rb_aligned = true; rb_aligned >= (samples > 1 ? true : false); rb_aligned--) {
|
|
|
|
for (int pipe_aligned = true; pipe_aligned >= (samples > 1 ? true : false); pipe_aligned--) {
|
|
|
|
for (unsigned mrt_index = 0; mrt_index < 2; mrt_index++) {
|
|
|
|
unsigned depth = 2;
|
|
|
|
char test[256];
|
|
|
|
|
|
|
|
snprintf(test, sizeof(test), "%ux%ux%u %ubpp %u samples rb:%u pipe:%u",
|
|
|
|
width, height, depth, bpp, samples, rb_aligned, pipe_aligned);
|
|
|
|
|
|
|
|
if (one_dcc_address_test(name, test, addrlib, info, width, height, depth, samples,
|
|
|
|
bpp, swizzle_modes[swizzle_mode], pipe_aligned,
|
|
|
|
rb_aligned, mrt_index, 0, 0, 0, 0)) {
|
|
|
|
} else {
|
|
|
|
local_fails++;
|
|
|
|
}
|
|
|
|
local_total++;
|
2021-03-19 19:52:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ac_addrlib_destroy(ac_addrlib);
|
|
|
|
p_atomic_add(&fails, local_fails);
|
|
|
|
p_atomic_add(&total, local_total);
|
|
|
|
}
|
|
|
|
printf("%16s total: %u, fail: %u\n", name, total, fails);
|
|
|
|
}
|
|
|
|
|
2021-04-06 09:48:41 +01:00
|
|
|
/* HTILE address computation without mipmapping. */
|
|
|
|
static unsigned gfx10_htile_addr_from_coord(const struct radeon_info *info,
|
|
|
|
const uint16_t *equation,
|
|
|
|
unsigned meta_block_width,
|
|
|
|
unsigned meta_block_height,
|
|
|
|
unsigned htile_pitch, unsigned htile_slice_size,
|
|
|
|
unsigned x, unsigned y, unsigned z,
|
|
|
|
unsigned pipe_xor)
|
|
|
|
{
|
|
|
|
unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
|
|
|
|
unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
|
|
|
|
unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 - 4;
|
|
|
|
|
|
|
|
return gfx10_meta_addr_from_coord(info, equation,
|
|
|
|
meta_block_width, meta_block_height,
|
|
|
|
blkSizeLog2,
|
|
|
|
htile_pitch, htile_slice_size,
|
2021-08-03 12:29:52 +01:00
|
|
|
x, y, z, pipe_xor, NULL);
|
2021-04-06 09:48:41 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool one_htile_address_test(const char *name, const char *test, ADDR_HANDLE addrlib,
|
|
|
|
const struct radeon_info *info,
|
|
|
|
unsigned width, unsigned height, unsigned depth,
|
|
|
|
unsigned bpp, unsigned swizzle_mode,
|
|
|
|
unsigned start_x, unsigned start_y, unsigned start_z)
|
|
|
|
{
|
|
|
|
ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
|
|
|
|
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
|
|
|
|
ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
|
|
|
|
ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
|
|
|
|
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT in = {0};
|
|
|
|
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT out = {0};
|
|
|
|
ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0};
|
|
|
|
|
|
|
|
hout.pMipInfo = meta_mip_info;
|
|
|
|
|
|
|
|
/* Compute HTILE info. */
|
|
|
|
hin.hTileFlags.pipeAligned = 1;
|
|
|
|
hin.hTileFlags.rbAligned = 1;
|
|
|
|
hin.depthFlags.depth = 1;
|
|
|
|
hin.depthFlags.texture = 1;
|
|
|
|
hin.depthFlags.opt4space = 1;
|
|
|
|
hin.swizzleMode = in.swizzleMode = xin.swizzleMode = swizzle_mode;
|
|
|
|
hin.unalignedWidth = in.unalignedWidth = width;
|
|
|
|
hin.unalignedHeight = in.unalignedHeight = height;
|
|
|
|
hin.numSlices = in.numSlices = depth;
|
|
|
|
hin.numMipLevels = in.numMipLevels = 1; /* addrlib can't do HtileAddrFromCoord with mipmapping. */
|
|
|
|
hin.firstMipIdInTail = 1;
|
|
|
|
|
|
|
|
int ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout);
|
|
|
|
assert(ret == ADDR_OK);
|
|
|
|
|
|
|
|
/* Compute xor. */
|
|
|
|
static AddrFormat format[] = {
|
|
|
|
ADDR_FMT_8, /* unused */
|
|
|
|
ADDR_FMT_16,
|
|
|
|
ADDR_FMT_32,
|
|
|
|
};
|
|
|
|
xin.flags = hin.depthFlags;
|
|
|
|
xin.resourceType = ADDR_RSRC_TEX_2D;
|
|
|
|
xin.format = format[util_logbase2(bpp / 8)];
|
|
|
|
xin.numFrags = xin.numSamples = in.numSamples = 1;
|
|
|
|
|
|
|
|
ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
|
|
|
|
assert(ret == ADDR_OK);
|
|
|
|
|
|
|
|
in.hTileFlags = hin.hTileFlags;
|
|
|
|
in.depthflags = xin.flags;
|
|
|
|
in.bpp = bpp;
|
|
|
|
in.pipeXor = xout.pipeBankXor;
|
|
|
|
|
|
|
|
for (in.x = start_x; in.x < width; in.x++) {
|
|
|
|
for (in.y = start_y; in.y < height; in.y++) {
|
|
|
|
for (in.slice = start_z; in.slice < depth; in.slice++) {
|
|
|
|
int r = Addr2ComputeHtileAddrFromCoord(addrlib, &in, &out);
|
|
|
|
if (r != ADDR_OK) {
|
|
|
|
printf("%s addrlib error: %s\n", name, test);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned addr =
|
|
|
|
gfx10_htile_addr_from_coord(info, hout.equation.gfx10_bits,
|
|
|
|
hout.metaBlkWidth, hout.metaBlkHeight,
|
|
|
|
hout.pitch, hout.sliceSize,
|
|
|
|
in.x, in.y, in.slice, in.pipeXor);
|
|
|
|
if (out.addr != addr) {
|
|
|
|
printf("%s fail (%s) at %ux%ux%u: expected = %llu, got = %u\n",
|
|
|
|
name, test, in.x, in.y, in.slice, out.addr, addr);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void run_htile_address_test(const char *name, const struct radeon_info *info, bool full)
|
|
|
|
{
|
|
|
|
unsigned total = 0;
|
|
|
|
unsigned fails = 0;
|
2021-05-07 01:41:47 +01:00
|
|
|
unsigned first_size = 0, last_size = 6*6 - 1;
|
|
|
|
unsigned swizzle_modes[2], num_swizzle_modes = 0;
|
|
|
|
|
|
|
|
switch (info->chip_class) {
|
|
|
|
case GFX9:
|
|
|
|
case GFX10:
|
|
|
|
case GFX10_3:
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_Z_X;
|
|
|
|
break;
|
|
|
|
case GFX11:
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_64KB_Z_X;
|
|
|
|
swizzle_modes[num_swizzle_modes++] = ADDR_SW_256KB_Z_X;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("unhandled gfx version");
|
|
|
|
}
|
2021-04-06 09:48:41 +01:00
|
|
|
|
|
|
|
/* The test coverage is reduced for Gitlab CI because it timeouts. */
|
|
|
|
if (!full) {
|
|
|
|
first_size = last_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef HAVE_OPENMP
|
|
|
|
#pragma omp parallel for
|
|
|
|
#endif
|
|
|
|
for (unsigned size = first_size; size <= last_size; size++) {
|
|
|
|
unsigned width = 8 + 379 * (size % 6);
|
|
|
|
unsigned height = 8 + 379 * (size / 6);
|
|
|
|
|
|
|
|
struct ac_addrlib *ac_addrlib = ac_addrlib_create(info, NULL);
|
|
|
|
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
|
|
|
|
|
2021-05-07 01:41:47 +01:00
|
|
|
for (unsigned swizzle_mode = 0; swizzle_mode < num_swizzle_modes; swizzle_mode++) {
|
|
|
|
for (unsigned depth = 1; depth <= 2; depth *= 2) {
|
|
|
|
for (unsigned bpp = 16; bpp <= 32; bpp *= 2) {
|
|
|
|
if (one_htile_address_test(name, name, addrlib, info, width, height, depth,
|
|
|
|
bpp, swizzle_modes[swizzle_mode], 0, 0, 0)) {
|
|
|
|
} else {
|
|
|
|
p_atomic_inc(&fails);
|
|
|
|
}
|
|
|
|
p_atomic_inc(&total);
|
2021-04-06 09:48:41 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ac_addrlib_destroy(ac_addrlib);
|
|
|
|
}
|
|
|
|
printf("%16s total: %u, fail: %u\n", name, total, fails);
|
|
|
|
}
|
2021-07-30 12:41:53 +01:00
|
|
|
|
2021-08-03 12:29:52 +01:00
|
|
|
/* CMASK address computation without mipmapping and MSAA. */
|
|
|
|
static unsigned gfx10_cmask_addr_from_coord(const struct radeon_info *info,
|
|
|
|
/* Shader key inputs: */
|
|
|
|
/* equation varies with bpp and pipe_aligned */
|
|
|
|
const uint16_t *equation, unsigned bpp,
|
|
|
|
unsigned meta_block_width, unsigned meta_block_height,
|
|
|
|
/* Shader inputs: */
|
|
|
|
unsigned cmask_pitch, unsigned cmask_slice_size,
|
|
|
|
unsigned x, unsigned y, unsigned z,
|
|
|
|
unsigned pipe_xor,
|
|
|
|
/* Shader outputs: */
|
|
|
|
unsigned *bit_position)
|
|
|
|
|
|
|
|
{
|
|
|
|
unsigned meta_block_width_log2 = util_logbase2(meta_block_width);
|
|
|
|
unsigned meta_block_height_log2 = util_logbase2(meta_block_height);
|
|
|
|
unsigned blkSizeLog2 = meta_block_width_log2 + meta_block_height_log2 - 7;
|
|
|
|
|
|
|
|
return gfx10_meta_addr_from_coord(info, equation,
|
|
|
|
meta_block_width, meta_block_height,
|
|
|
|
blkSizeLog2,
|
|
|
|
cmask_pitch, cmask_slice_size,
|
|
|
|
x, y, z, pipe_xor, bit_position);
|
|
|
|
}
|
|
|
|
|
2021-07-30 12:41:53 +01:00
|
|
|
static bool one_cmask_address_test(const char *name, const char *test, ADDR_HANDLE addrlib,
|
|
|
|
const struct radeon_info *info,
|
|
|
|
unsigned width, unsigned height, unsigned depth,
|
|
|
|
unsigned bpp, unsigned swizzle_mode,
|
|
|
|
bool pipe_aligned, bool rb_aligned, unsigned mrt_index,
|
|
|
|
unsigned start_x, unsigned start_y, unsigned start_z)
|
|
|
|
{
|
|
|
|
ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {sizeof(xin)};
|
|
|
|
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {sizeof(xout)};
|
|
|
|
ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {sizeof(cin)};
|
|
|
|
ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {sizeof(cout)};
|
|
|
|
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT in = {sizeof(in)};
|
|
|
|
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT out = {sizeof(out)};
|
|
|
|
|
|
|
|
/* Compute CMASK info. */
|
|
|
|
cin.resourceType = xin.resourceType = in.resourceType = ADDR_RSRC_TEX_2D;
|
|
|
|
cin.swizzleMode = xin.swizzleMode = in.swizzleMode = swizzle_mode;
|
|
|
|
cin.unalignedWidth = in.unalignedWidth = width;
|
|
|
|
cin.unalignedHeight = in.unalignedHeight = height;
|
|
|
|
cin.numSlices = in.numSlices = depth;
|
|
|
|
cin.numMipLevels = 1;
|
|
|
|
cin.firstMipIdInTail = 1;
|
|
|
|
cin.cMaskFlags.pipeAligned = pipe_aligned;
|
|
|
|
cin.cMaskFlags.rbAligned = rb_aligned;
|
|
|
|
cin.cMaskFlags.linear = false;
|
|
|
|
cin.colorFlags.color = 1;
|
|
|
|
cin.colorFlags.texture = 1;
|
|
|
|
cin.colorFlags.opt4space = 1;
|
|
|
|
cin.colorFlags.metaRbUnaligned = !rb_aligned;
|
|
|
|
cin.colorFlags.metaPipeUnaligned = !pipe_aligned;
|
|
|
|
|
|
|
|
int ret = Addr2ComputeCmaskInfo(addrlib, &cin, &cout);
|
|
|
|
assert(ret == ADDR_OK);
|
|
|
|
|
|
|
|
/* Compute xor. */
|
|
|
|
static AddrFormat format[] = {
|
|
|
|
ADDR_FMT_8,
|
|
|
|
ADDR_FMT_16,
|
|
|
|
ADDR_FMT_32,
|
|
|
|
ADDR_FMT_32_32,
|
|
|
|
ADDR_FMT_32_32_32_32,
|
|
|
|
};
|
|
|
|
xin.flags = cin.colorFlags;
|
|
|
|
xin.format = format[util_logbase2(bpp / 8)];
|
|
|
|
xin.surfIndex = mrt_index;
|
|
|
|
xin.numSamples = in.numSamples = xin.numFrags = in.numFrags = 1;
|
|
|
|
|
|
|
|
ret = Addr2ComputePipeBankXor(addrlib, &xin, &xout);
|
|
|
|
assert(ret == ADDR_OK);
|
|
|
|
|
|
|
|
in.cMaskFlags = cin.cMaskFlags;
|
|
|
|
in.colorFlags = cin.colorFlags;
|
|
|
|
in.pipeXor = xout.pipeBankXor;
|
|
|
|
|
|
|
|
for (in.x = start_x; in.x < width; in.x++) {
|
|
|
|
for (in.y = start_y; in.y < height; in.y++) {
|
|
|
|
for (in.slice = start_z; in.slice < depth; in.slice++) {
|
|
|
|
int r = Addr2ComputeCmaskAddrFromCoord(addrlib, &in, &out);
|
|
|
|
if (r != ADDR_OK) {
|
|
|
|
printf("%s addrlib error: %s\n", name, test);
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned addr, bit_position;
|
|
|
|
|
2021-08-03 12:29:52 +01:00
|
|
|
if (info->chip_class == GFX9) {
|
|
|
|
addr = gfx9_meta_addr_from_coord(info, &cout.equation.gfx9,
|
|
|
|
cout.metaBlkWidth, cout.metaBlkHeight, 1,
|
|
|
|
cout.pitch, cout.height,
|
|
|
|
in.x, in.y, in.slice, 0, in.pipeXor,
|
|
|
|
&bit_position);
|
|
|
|
} else {
|
|
|
|
addr = gfx10_cmask_addr_from_coord(info, cout.equation.gfx10_bits,
|
|
|
|
bpp, cout.metaBlkWidth,
|
|
|
|
cout.metaBlkHeight,
|
|
|
|
cout.pitch, cout.sliceSize,
|
|
|
|
in.x, in.y, in.slice,
|
|
|
|
in.pipeXor,
|
|
|
|
&bit_position);
|
|
|
|
}
|
2021-07-30 12:41:53 +01:00
|
|
|
|
|
|
|
if (out.addr != addr || out.bitPosition != bit_position) {
|
|
|
|
printf("%s fail (%s) at %ux%ux%u: expected (addr) = %llu, got = %u, "
|
|
|
|
"expected (bit_position) = %u, got = %u\n",
|
|
|
|
name, test, in.x, in.y, in.slice, out.addr, addr,
|
|
|
|
out.bitPosition, bit_position);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void run_cmask_address_test(const char *name, const struct radeon_info *info, bool full)
|
|
|
|
{
|
|
|
|
unsigned total = 0;
|
|
|
|
unsigned fails = 0;
|
2021-08-03 12:29:52 +01:00
|
|
|
unsigned swizzle_mode = info->chip_class == GFX9 ? ADDR_SW_64KB_S_X : ADDR_SW_64KB_Z_X;
|
2021-07-30 12:41:53 +01:00
|
|
|
unsigned first_size = 0, last_size = 6*6 - 1, max_bpp = 32;
|
|
|
|
|
2021-05-07 01:41:47 +01:00
|
|
|
/* GFX11 doesn't have CMASK. */
|
|
|
|
if (info->chip_class >= GFX11)
|
|
|
|
return;
|
|
|
|
|
2021-07-30 12:41:53 +01:00
|
|
|
/* The test coverage is reduced for Gitlab CI because it timeouts. */
|
|
|
|
if (!full) {
|
|
|
|
first_size = last_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef HAVE_OPENMP
|
|
|
|
#pragma omp parallel for
|
|
|
|
#endif
|
|
|
|
for (unsigned size = first_size; size <= last_size; size++) {
|
|
|
|
unsigned width = 8 + 379 * (size % 6);
|
|
|
|
unsigned height = 8 + 379 * (size / 6);
|
|
|
|
|
|
|
|
struct ac_addrlib *ac_addrlib = ac_addrlib_create(info, NULL);
|
|
|
|
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
|
|
|
|
|
|
|
|
for (unsigned depth = 1; depth <= 2; depth *= 2) {
|
|
|
|
for (unsigned bpp = 16; bpp <= max_bpp; bpp *= 2) {
|
|
|
|
for (int rb_aligned = true; rb_aligned >= true; rb_aligned--) {
|
|
|
|
for (int pipe_aligned = true; pipe_aligned >= true; pipe_aligned--) {
|
|
|
|
if (one_cmask_address_test(name, name, addrlib, info,
|
|
|
|
width, height, depth, bpp,
|
2021-08-03 12:29:52 +01:00
|
|
|
swizzle_mode,
|
2021-07-30 12:41:53 +01:00
|
|
|
pipe_aligned, rb_aligned,
|
|
|
|
0, 0, 0, 0)) {
|
|
|
|
} else {
|
|
|
|
p_atomic_inc(&fails);
|
|
|
|
}
|
|
|
|
p_atomic_inc(&total);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ac_addrlib_destroy(ac_addrlib);
|
|
|
|
}
|
|
|
|
printf("%16s total: %u, fail: %u\n", name, total, fails);
|
|
|
|
}
|
|
|
|
|
2021-03-19 19:52:44 +00:00
|
|
|
int main(int argc, char **argv)
|
|
|
|
{
|
|
|
|
bool full = false;
|
|
|
|
|
|
|
|
if (argc == 2 && !strcmp(argv[1], "--full"))
|
|
|
|
full = true;
|
|
|
|
else
|
|
|
|
puts("Specify --full to run the full test.");
|
|
|
|
|
2021-04-06 09:48:41 +01:00
|
|
|
puts("DCC:");
|
2021-03-19 19:52:44 +00:00
|
|
|
for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
|
|
|
|
struct radeon_info info = get_radeon_info(&testcases[i]);
|
|
|
|
|
|
|
|
run_dcc_address_test(testcases[i].name, &info, full);
|
|
|
|
}
|
|
|
|
|
2021-04-06 09:48:41 +01:00
|
|
|
puts("HTILE:");
|
|
|
|
for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
|
|
|
|
struct radeon_info info = get_radeon_info(&testcases[i]);
|
|
|
|
|
|
|
|
/* Only GFX10+ is currently supported. */
|
|
|
|
if (info.chip_class < GFX10)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
run_htile_address_test(testcases[i].name, &info, full);
|
|
|
|
}
|
|
|
|
|
2021-07-30 12:41:53 +01:00
|
|
|
puts("CMASK:");
|
|
|
|
for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
|
|
|
|
struct radeon_info info = get_radeon_info(&testcases[i]);
|
|
|
|
|
|
|
|
run_cmask_address_test(testcases[i].name, &info, full);
|
|
|
|
}
|
|
|
|
|
2021-03-19 19:52:44 +00:00
|
|
|
return 0;
|
|
|
|
}
|