339 lines
11 KiB
C
339 lines
11 KiB
C
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/*
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* Copyright © 2019 Google LLC
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "tu_private.h"
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#include "spirv/nir_spirv.h"
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#include "util/mesa-sha1.h"
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#include "ir3/ir3_nir.h"
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static nir_function *
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tu_spirv_to_nir(struct ir3_compiler *compiler,
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const uint32_t *words,
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size_t word_count,
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gl_shader_stage stage,
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const char *entry_point_name,
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const VkSpecializationInfo *spec_info)
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{
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/* TODO these are made-up */
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const struct spirv_to_nir_options spirv_options = {
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.lower_workgroup_access_to_offsets = true,
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.lower_ubo_ssbo_access_to_offsets = true,
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.caps = { false },
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};
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const nir_shader_compiler_options *nir_options =
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ir3_get_compiler_options(compiler);
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/* convert VkSpecializationInfo */
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struct nir_spirv_specialization *spec = NULL;
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uint32_t num_spec = 0;
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if (spec_info && spec_info->mapEntryCount) {
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spec = malloc(sizeof(*spec) * spec_info->mapEntryCount);
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if (!spec)
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return NULL;
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for (uint32_t i = 0; i < spec_info->mapEntryCount; i++) {
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const VkSpecializationMapEntry *entry = &spec_info->pMapEntries[i];
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const void *data = spec_info->pData + entry->offset;
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assert(data + entry->size <= spec_info->pData + spec_info->dataSize);
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spec[i].id = entry->constantID;
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if (entry->size == 8)
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spec[i].data64 = *(const uint64_t *) data;
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else
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spec[i].data32 = *(const uint32_t *) data;
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spec[i].defined_on_module = false;
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}
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num_spec = spec_info->mapEntryCount;
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}
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nir_function *entry_point =
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spirv_to_nir(words, word_count, spec, num_spec, stage, entry_point_name,
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&spirv_options, nir_options);
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free(spec);
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assert(entry_point->shader->info.stage == stage);
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nir_validate_shader(entry_point->shader, "after spirv_to_nir");
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return entry_point;
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}
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static void
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tu_sort_variables_by_location(struct exec_list *variables)
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{
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struct exec_list sorted;
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exec_list_make_empty(&sorted);
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nir_foreach_variable_safe(var, variables)
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{
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exec_node_remove(&var->node);
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/* insert the variable into the sorted list */
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nir_variable *next = NULL;
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nir_foreach_variable(tmp, &sorted)
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{
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if (var->data.location < tmp->data.location) {
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next = tmp;
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break;
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}
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}
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if (next)
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exec_node_insert_node_before(&next->node, &var->node);
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else
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exec_list_push_tail(&sorted, &var->node);
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}
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exec_list_move_nodes_to(&sorted, variables);
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}
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struct tu_shader *
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tu_shader_create(struct tu_device *dev,
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gl_shader_stage stage,
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const VkPipelineShaderStageCreateInfo *stage_info,
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const VkAllocationCallbacks *alloc)
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{
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const struct tu_shader_module *module =
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tu_shader_module_from_handle(stage_info->module);
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struct tu_shader *shader;
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const uint32_t max_variant_count = (stage == MESA_SHADER_VERTEX) ? 2 : 1;
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shader = vk_zalloc2(
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&dev->alloc, alloc,
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sizeof(*shader) + sizeof(struct ir3_shader_variant) * max_variant_count,
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8, VK_SYSTEM_ALLOCATION_SCOPE_COMMAND);
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if (!shader)
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return NULL;
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/* translate SPIR-V to NIR */
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assert(module->code_size % 4 == 0);
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nir_function *entry_point = tu_spirv_to_nir(
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dev->compiler, (const uint32_t *) module->code, module->code_size / 4,
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stage, stage_info->pName, stage_info->pSpecializationInfo);
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if (!entry_point) {
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vk_free2(&dev->alloc, alloc, shader);
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return NULL;
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}
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nir_shader *nir = entry_point->shader;
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if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_NIR)) {
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fprintf(stderr, "translated nir:\n");
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nir_print_shader(nir, stderr);
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}
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/* TODO what needs to happen? */
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switch (stage) {
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case MESA_SHADER_VERTEX:
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tu_sort_variables_by_location(&nir->outputs);
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break;
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case MESA_SHADER_TESS_CTRL:
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case MESA_SHADER_TESS_EVAL:
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case MESA_SHADER_GEOMETRY:
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tu_sort_variables_by_location(&nir->inputs);
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tu_sort_variables_by_location(&nir->outputs);
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break;
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case MESA_SHADER_FRAGMENT:
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tu_sort_variables_by_location(&nir->inputs);
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break;
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case MESA_SHADER_COMPUTE:
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break;
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default:
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unreachable("invalid gl_shader_stage");
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break;
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}
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nir_assign_var_locations(&nir->inputs, &nir->num_inputs,
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ir3_glsl_type_size);
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nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
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ir3_glsl_type_size);
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nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
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ir3_glsl_type_size);
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NIR_PASS_V(nir, nir_lower_system_values);
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NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size, 0);
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nir_shader_gather_info(nir, entry_point->impl);
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shader->ir3_shader.compiler = dev->compiler;
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shader->ir3_shader.type = stage;
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shader->ir3_shader.nir = nir;
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return shader;
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}
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void
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tu_shader_destroy(struct tu_device *dev,
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struct tu_shader *shader,
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const VkAllocationCallbacks *alloc)
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{
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if (shader->ir3_shader.nir)
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ralloc_free(shader->ir3_shader.nir);
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for (uint32_t i = 0; i < 1 + shader->has_binning_pass; i++) {
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if (shader->variants[i].ir)
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ir3_destroy(shader->variants[i].ir);
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if (shader->variants[i].immediates)
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free(shader->variants[i].immediates);
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}
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if (shader->binary)
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free(shader->binary);
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if (shader->binning_binary)
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free(shader->binning_binary);
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vk_free2(&dev->alloc, alloc, shader);
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}
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void
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tu_shader_compile_options_init(
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struct tu_shader_compile_options *options,
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const VkGraphicsPipelineCreateInfo *pipeline_info)
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{
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*options = (struct tu_shader_compile_options) {
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/* TODO ir3_key */
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.optimize = !(pipeline_info->flags &
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VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT),
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.include_binning_pass = true,
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};
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}
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static uint32_t *
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tu_compile_shader_variant(struct ir3_shader *shader,
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const struct ir3_shader_key *key,
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bool binning_pass,
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struct ir3_shader_variant *variant)
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{
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variant->shader = shader;
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variant->type = shader->type;
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variant->key = *key;
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variant->binning_pass = binning_pass;
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int ret = ir3_compile_shader_nir(shader->compiler, variant);
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if (ret)
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return NULL;
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/* when assemble fails, we rely on tu_shader_destroy to clean up the
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* variant
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*/
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return ir3_shader_assemble(variant, shader->compiler->gpu_id);
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}
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VkResult
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tu_shader_compile(struct tu_device *dev,
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struct tu_shader *shader,
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const struct tu_shader *next_stage,
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const struct tu_shader_compile_options *options,
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const VkAllocationCallbacks *alloc)
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{
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if (options->optimize) {
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/* ignore the key for the first pass of optimization */
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ir3_optimize_nir(&shader->ir3_shader, shader->ir3_shader.nir, NULL);
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if (unlikely(dev->physical_device->instance->debug_flags &
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TU_DEBUG_NIR)) {
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fprintf(stderr, "optimized nir:\n");
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nir_print_shader(shader->ir3_shader.nir, stderr);
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}
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}
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shader->binary = tu_compile_shader_variant(
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&shader->ir3_shader, &options->key, false, &shader->variants[0]);
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if (!shader->binary)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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/* compile another variant for the binning pass */
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if (options->include_binning_pass &&
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shader->ir3_shader.type == MESA_SHADER_VERTEX) {
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shader->binning_binary = tu_compile_shader_variant(
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&shader->ir3_shader, &options->key, true, &shader->variants[1]);
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if (!shader->binning_binary)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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shader->has_binning_pass = true;
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}
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if (unlikely(dev->physical_device->instance->debug_flags & TU_DEBUG_IR3)) {
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fprintf(stderr, "disassembled ir3:\n");
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fprintf(stderr, "shader: %s\n",
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gl_shader_stage_name(shader->ir3_shader.type));
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ir3_shader_disasm(&shader->variants[0], shader->binary, stderr);
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if (shader->has_binning_pass) {
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fprintf(stderr, "disassembled ir3:\n");
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fprintf(stderr, "shader: %s (binning)\n",
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gl_shader_stage_name(shader->ir3_shader.type));
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ir3_shader_disasm(&shader->variants[1], shader->binning_binary,
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stderr);
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}
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}
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return VK_SUCCESS;
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}
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VkResult
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tu_CreateShaderModule(VkDevice _device,
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const VkShaderModuleCreateInfo *pCreateInfo,
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const VkAllocationCallbacks *pAllocator,
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VkShaderModule *pShaderModule)
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{
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TU_FROM_HANDLE(tu_device, device, _device);
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struct tu_shader_module *module;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
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assert(pCreateInfo->flags == 0);
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assert(pCreateInfo->codeSize % 4 == 0);
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module = vk_alloc2(&device->alloc, pAllocator,
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sizeof(*module) + pCreateInfo->codeSize, 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (module == NULL)
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return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
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module->code_size = pCreateInfo->codeSize;
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memcpy(module->code, pCreateInfo->pCode, pCreateInfo->codeSize);
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_mesa_sha1_compute(module->code, module->code_size, module->sha1);
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*pShaderModule = tu_shader_module_to_handle(module);
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return VK_SUCCESS;
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}
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void
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tu_DestroyShaderModule(VkDevice _device,
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VkShaderModule _module,
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const VkAllocationCallbacks *pAllocator)
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{
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TU_FROM_HANDLE(tu_device, device, _device);
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TU_FROM_HANDLE(tu_shader_module, module, _module);
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if (!module)
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return;
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vk_free2(&device->alloc, pAllocator, module);
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}
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