mesa/src/freedreno/isa/ir3-cat1.xml

<?xml version="1.0" encoding="UTF-8"?>
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
 -->

<isa>

<!--
	Cat1 Instruction(s):
 -->

<bitset name="#cat1-dst" size="8">
	<doc>
		Unlike other instruction categories, cat1 can have relative dest
	</doc>
	<override>
		<expr>
			({OFFSET} == 0) &amp;&amp; {DST_REL}
		</expr>
		<display>
			r&lt;a0.x&gt;
		</display>
		<field name="OFFSET" low="0" high="7" type="uint"/>
	</override>
	<override>
		<expr>
			{DST_REL}
		</expr>
		<display>
			r&lt;a0.x + {OFFSET}&gt;
		</display>
		<field name="OFFSET" low="0" high="7" type="uint"/>
	</override>
	<display>
		{DST}
	</display>
	<field name="DST" low="0" high="7" type="#reg-gpr"/>
	<encode type="struct ir3_register *">
		<map name="DST">src</map>
		<map name="OFFSET">src->array.offset</map>
	</encode>
</bitset>

<bitset name="#instruction-cat1" extends="#instruction">
	<field name="DST" low="32" high="39" type="#cat1-dst">
		<param name="DST_REL"/>
	</field>
	<field name="REPEAT" low="40" high="42" type="#rptN"/>
	<field name="SS" pos="44" type="bool" display="(ss)"/>
	<field name="UL" pos="45" type="bool" display="(ul)"/>
	<field name="DST_REL" pos="49" type="bool"/>
	<field name="EVEN" pos="55" type="bool" display="(even)"/>
	<field name="POS_INF" pos="56" type="bool" display="(pos_infinity)"/>
	<field name="JP" pos="59" type="bool" display="(jp)"/>
	<field name="SY" pos="60" type="bool" display="(sy)"/>
	<pattern low="61" high="63">001</pattern>  <!-- cat1 -->
	<encode>
		<map name="SRC">src->regs[1]</map>
		<map name="SRC_R">!!(src->regs[1]->flags &amp; IR3_REG_R)</map>
		<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
		<map name="DST_TYPE">src->cat1.dst_type</map>
		<map name="DST_REL">!!(src->regs[0]->flags &amp; IR3_REG_RELATIV)</map>
		<map name="SRC_TYPE">src->cat1.src_type</map>
		<map name="EVEN">!!(src->regs[0]->flags &amp; IR3_REG_EVEN)</map>
		<map name="POS_INF">!!(src->regs[0]->flags &amp; IR3_REG_POS_INF)</map>
	</encode>
</bitset>

<bitset name="#instruction-cat1-mov" extends="#instruction-cat1">
	<override>
		<expr>
			({DST} == 0xf4 /* a0.x */) &amp;&amp; ({SRC_TYPE} == 4 /* s16 */) &amp;&amp; ({DST_TYPE} == 4)
		</expr>
		<display>
			{SY}{SS}{JP}{REPEAT}{UL}mova {EVEN}{POS_INF}a0.x, {SRC}
		</display>
		<assert low="32" high="39">11110100</assert>  <!-- DST==a0.x -->
		<assert low="46" high="48">100</assert>       <!-- DST_TYPE==s16 -->
		<assert low="50" high="52">100</assert>       <!-- SRC_TYPE==s16 -->
	</override>
	<override>
		<expr>
			({DST} == 0xf5 /* a0.y */) &amp;&amp; ({SRC_TYPE} == 2 /* u16 */) &amp;&amp; ({DST_TYPE} == 2)
		</expr>
		<display>
			{SY}{SS}{JP}{REPEAT}{UL}mova1 {EVEN}{POS_INF}a1.x, {SRC}
		</display>
		<assert low="32" high="39">11110101</assert>  <!-- DST==a0.y -->
		<assert low="46" high="48">010</assert>       <!-- DST_TYPE==u16 -->
		<assert low="50" high="52">010</assert>       <!-- SRC_TYPE==u16 -->
	</override>
	<override>
		<expr>
			{SRC_TYPE} != {DST_TYPE}
		</expr>
		<display>
			{SY}{SS}{JP}{REPEAT}{UL}cov.{SRC_TYPE}{DST_TYPE} {EVEN}{POS_INF}{DST_HALF}{DST}, {SRC}
		</display>
	</override>
	<display>
		{SY}{SS}{JP}{REPEAT}{UL}mov.{SRC_TYPE}{DST_TYPE} {EVEN}{POS_INF}{DST_HALF}{DST}, {SRC}
	</display>
	<pattern low="57" high="58">00</pattern>  <!-- OPC -->
	<derived name="HALF" type="bool" display="h">
		<expr>
			({SRC_TYPE} == 0) /* f16 */ ||
			({SRC_TYPE} == 2) /* u16 */ ||
			({SRC_TYPE} == 4) /* s16 */ ||
			({SRC_TYPE} == 6) /* u8 */  ||
			({SRC_TYPE} == 7) /* s8 */
		</expr>
	</derived>
	<derived name="DST_HALF" type="bool" display="h">
		<expr>
			({DST_TYPE} == 0) /* f16 */ ||
			({DST_TYPE} == 2) /* u16 */ ||
			({DST_TYPE} == 4) /* s16 */ ||
			({DST_TYPE} == 6) /* u8 */  ||
			({DST_TYPE} == 7) /* s8 */
		</expr>
	</derived>
	<field name="DST_TYPE" low="46" high="48" type="#type"/>
	<field name="SRC_TYPE" low="50" high="52" type="#type"/>
</bitset>

<!--
	Helpers for displaying cat1 source forms.. split out so the toplevel
	instruction can just refer to {SRC}.  This decouples the cov/mov/mova
	permultations from the different src type permutations
 -->

<bitset name="#cat1-immed-src" size="32">
	<override>
		<expr>
			{SRC_TYPE} == 0 /* f16 */
		</expr>
		<display>
			h({IMMED})
		</display>
		<field name="IMMED" low="0" high="15" type="float"/>
	</override>
	<override>
		<expr>
			{SRC_TYPE} == 1 /* f32 */
		</expr>
		<display>
			({IMMED})
		</display>
		<field name="IMMED" low="0" high="31" type="float"/>
	</override>
	<override>
		<expr>
			({SRC_TYPE} == 3 /* u32 */) &amp;&amp; ({IMMED} > 0x1000)
		</expr>
		<display>
			0x{IMMED}
		</display>
		<field name="IMMED" low="0" high="31" type="hex"/>
	</override>
	<override>
		<expr>
			{SRC_TYPE} == 4 /* s16 */
		</expr>
		<field name="IMMED" low="0" high="15" type="int"/>
	</override>
	<override>
		<expr>
			{SRC_TYPE} == 5 /* s32 */
		</expr>
		<field name="IMMED" low="0" high="31" type="int"/>
	</override>

	<display>
		{IMMED}
	</display>

	<field name="IMMED" low="0" high="31" type="uint"/>
	<encode type="struct ir3_register *">
		<map name="IMMED">src->uim_val</map>
	</encode>
</bitset>

<bitset name="#cat1-const-src" size="11">
	<display>
		{SRC_R}{HALF}{CONST}
	</display>
	<field name="CONST" low="0" high="10" type="#reg-const"/>
	<encode type="struct ir3_register *">
		<map name="CONST">src</map>
	</encode>
</bitset>

<bitset name="#cat1-gpr-src" size="8">
	<display>
		{SRC_R}{HALF}{SRC}
	</display>
	<field name="SRC" low="0" high="7" type="#reg-gpr"/>
	<encode type="struct ir3_register *">
		<map name="SRC">src</map>
	</encode>
</bitset>

<bitset name="#cat1-relative-gpr-src" size="10">
	<display>
		{SRC_R}{HALF}{SRC}
	</display>
	<field name="SRC" low="0" high="9" type="#reg-relative-gpr"/>
	<encode type="struct ir3_register *">
		<map name="SRC">src</map>
	</encode>
</bitset>

<bitset name="#cat1-relative-const-src" size="10">
	<display>
		{SRC_R}{HALF}{SRC}
	</display>
	<field name="SRC" low="0" high="9" type="#reg-relative-const"/>
	<encode type="struct ir3_register *">
		<map name="SRC">src</map>
	</encode>
</bitset>

<!--
	cov/mov/mova permutations based on src type:
 -->

<bitset name="mov-immed" extends="#instruction-cat1-mov">
	<field name="SRC" low="0" high="31" type="#cat1-immed-src">
		<param name="SRC_TYPE"/>
	</field>
	<pattern pos="43">0</pattern>   <!-- SRC_R -->
	<pattern low="53" high="54">10</pattern>
</bitset>

<bitset name="mov-const" extends="#instruction-cat1-mov">
	<field name="SRC" low="0" high="10" type="#cat1-const-src">
		<param name="SRC_R"/>
		<param name="HALF"/>
	</field>
	<pattern low="11" high="31">000000000000000000000</pattern>
	<field name="SRC_R" pos="43" type="bool" display="(r)"/>
	<pattern low="53" high="54">01</pattern>
</bitset>

<bitset name="mov-gpr" extends="#instruction-cat1-mov">
	<field name="SRC" low="0" high="7" type="#cat1-gpr-src">
		<param name="SRC_R"/>
		<param name="HALF"/>
	</field>
	<pattern low="8" high="31">000000000000000000000000</pattern>
	<field name="SRC_R" pos="43" type="bool" display="(r)"/>
	<pattern low="53" high="54">00</pattern>
</bitset>

<bitset name="#instruction-cat1-relative" extends="#instruction-cat1-mov">
	<pattern pos="11">1</pattern>
	<pattern low="12" high="31">00000000000000000000</pattern>
	<field name="SRC_R" pos="43" type="bool" display="(r)"/>
	<pattern low="53" high="54">00</pattern>
</bitset>

<bitset name="mov-relgpr" extends="#instruction-cat1-relative">
	<field name="SRC" low="0" high="9" type="#cat1-relative-gpr-src">
		<param name="SRC_R"/>
		<param name="HALF"/>
	</field>
	<pattern pos="10">0</pattern>
</bitset>

<bitset name="mov-relconst" extends="#instruction-cat1-relative">
	<field name="SRC" low="0" high="9" type="#cat1-relative-const-src">
		<param name="SRC_R"/>
		<param name="HALF"/>
	</field>
	<pattern pos="10">1</pattern>
</bitset>

<!--
	Other newer cat1 instructions
 -->

<bitset name="movmsk" extends="#instruction-cat1">
	<display>
		{SY}{SS}{JP}{UL}movmsk.w{W} {DST}
	</display>
	<derived name="W" type="uint">
		<expr>
			({REPEAT} + 1) * 32
		</expr>
	</derived>
	<pattern low="0" high="31">00000000000000000000000000000000</pattern>
	<pattern pos="43">0</pattern>   <!-- SRC_R -->
	<pattern low="46" high="48">011</pattern>       <!-- DST_TYPE==u32 -->
	<pattern low="50" high="52">011</pattern>       <!-- SRC_TYPE==u32 -->
	<pattern low="53" high="54">00</pattern>
	<pattern low="57" high="58">11</pattern>  <!-- OPC -->

	<!--
		TODO in ir3 things are encoded w/ instr->repeat==0 and repeat field is
		reconstructed from wrmask.. but I'm not sure if that is actually accurate
		(in terms of how delay slots work).. for now, work around that to match
		the existing stuff:
	 -->
	<encode>
		<map name="REPEAT">util_last_bit(src->regs[0]->wrmask) - 1</map>
	</encode>
</bitset>


</isa>