2015-07-15 20:09:52 +01:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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2015-07-17 23:04:27 +01:00
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#include "anv_private.h"
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2015-07-15 20:09:52 +01:00
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/** \file anv_cmd_buffer.c
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*
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2015-07-30 22:59:02 +01:00
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* This file contains all of the stuff for emitting commands into a command
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* buffer. This includes implementations of most of the vkCmd*
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* entrypoints. This file is concerned entirely with state emission and
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* not with the command buffer data structure itself. As far as this file
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* is concerned, most of anv_cmd_buffer is magic.
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2015-07-15 20:09:52 +01:00
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*/
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2015-07-30 22:59:02 +01:00
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static void
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anv_cmd_state_init(struct anv_cmd_state *state)
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2015-07-15 20:09:52 +01:00
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{
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2015-07-30 22:59:02 +01:00
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state->rs_state = NULL;
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state->vp_state = NULL;
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state->cb_state = NULL;
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state->ds_state = NULL;
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memset(&state->state_vf, 0, sizeof(state->state_vf));
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memset(&state->descriptors, 0, sizeof(state->descriptors));
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state->dirty = 0;
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state->vb_dirty = 0;
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state->descriptors_dirty = 0;
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state->pipeline = NULL;
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state->vp_state = NULL;
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state->rs_state = NULL;
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state->ds_state = NULL;
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}
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2015-07-29 22:05:06 +01:00
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2015-07-30 22:59:02 +01:00
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VkResult anv_CreateCommandBuffer(
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VkDevice _device,
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const VkCmdBufferCreateInfo* pCreateInfo,
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VkCmdBuffer* pCmdBuffer)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_cmd_pool, pool, pCreateInfo->cmdPool);
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struct anv_cmd_buffer *cmd_buffer;
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VkResult result;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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cmd_buffer = anv_device_alloc(device, sizeof(*cmd_buffer), 8,
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VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
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if (cmd_buffer == NULL)
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2015-07-15 20:09:52 +01:00
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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2015-07-30 22:59:02 +01:00
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cmd_buffer->device = device;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
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if (result != VK_SUCCESS)
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goto fail;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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anv_state_stream_init(&cmd_buffer->surface_state_stream,
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&device->surface_state_block_pool);
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anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
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&device->dynamic_state_block_pool);
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cmd_buffer->level = pCreateInfo->level;
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cmd_buffer->opt_flags = 0;
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anv_cmd_state_init(&cmd_buffer->state);
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list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
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*pCmdBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
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2015-07-29 22:05:06 +01:00
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2015-07-15 20:09:52 +01:00
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return VK_SUCCESS;
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2015-07-30 22:59:02 +01:00
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fail: anv_device_free(device, cmd_buffer);
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return result;
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2015-07-15 20:09:52 +01:00
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}
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2015-07-30 22:59:02 +01:00
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VkResult anv_DestroyCommandBuffer(
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VkDevice _device,
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VkCmdBuffer _cmd_buffer)
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2015-07-29 22:05:06 +01:00
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{
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2015-07-30 22:59:02 +01:00
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ANV_FROM_HANDLE(anv_device, device, _device);
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, _cmd_buffer);
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list_del(&cmd_buffer->pool_link);
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anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
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anv_state_stream_finish(&cmd_buffer->surface_state_stream);
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anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
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anv_device_free(device, cmd_buffer);
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return VK_SUCCESS;
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}
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VkResult anv_ResetCommandBuffer(
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VkCmdBuffer cmdBuffer,
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VkCmdBufferResetFlags flags)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
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anv_cmd_state_init(&cmd_buffer->state);
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return VK_SUCCESS;
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2015-07-29 22:05:06 +01:00
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}
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2015-07-15 20:09:52 +01:00
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void
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2015-07-30 22:59:02 +01:00
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anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
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2015-07-15 20:09:52 +01:00
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{
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2015-07-30 22:59:02 +01:00
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struct anv_device *device = cmd_buffer->device;
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struct anv_bo *scratch_bo = NULL;
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2015-08-03 09:18:09 +01:00
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cmd_buffer->state.scratch_size =
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anv_block_pool_size(&device->scratch_block_pool);
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2015-07-30 22:59:02 +01:00
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if (cmd_buffer->state.scratch_size > 0)
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scratch_bo = &device->scratch_block_pool.bo;
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anv_batch_emit(&cmd_buffer->batch, GEN8_STATE_BASE_ADDRESS,
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.GeneralStateBaseAddress = { scratch_bo, 0 },
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.GeneralStateMemoryObjectControlState = GEN8_MOCS,
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.GeneralStateBaseAddressModifyEnable = true,
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.GeneralStateBufferSize = 0xfffff,
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.GeneralStateBufferSizeModifyEnable = true,
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.SurfaceStateBaseAddress = { anv_cmd_buffer_current_surface_bo(cmd_buffer), 0 },
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.SurfaceStateMemoryObjectControlState = GEN8_MOCS,
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.SurfaceStateBaseAddressModifyEnable = true,
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.DynamicStateBaseAddress = { &device->dynamic_state_block_pool.bo, 0 },
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.DynamicStateMemoryObjectControlState = GEN8_MOCS,
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.DynamicStateBaseAddressModifyEnable = true,
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.DynamicStateBufferSize = 0xfffff,
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.DynamicStateBufferSizeModifyEnable = true,
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.IndirectObjectBaseAddress = { NULL, 0 },
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.IndirectObjectMemoryObjectControlState = GEN8_MOCS,
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.IndirectObjectBaseAddressModifyEnable = true,
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.IndirectObjectBufferSize = 0xfffff,
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.IndirectObjectBufferSizeModifyEnable = true,
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.InstructionBaseAddress = { &device->instruction_block_pool.bo, 0 },
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.InstructionMemoryObjectControlState = GEN8_MOCS,
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.InstructionBaseAddressModifyEnable = true,
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.InstructionBufferSize = 0xfffff,
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.InstructionBuffersizeModifyEnable = true);
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/* After re-setting the surface state base address, we have to do some
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* cache flusing so that the sampler engine will pick up the new
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* SURFACE_STATE objects and binding tables. From the Broadwell PRM,
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* Shared Function > 3D Sampler > State > State Caching (page 96):
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*
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* Coherency with system memory in the state cache, like the texture
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* cache is handled partially by software. It is expected that the
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* command stream or shader will issue Cache Flush operation or
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* Cache_Flush sampler message to ensure that the L1 cache remains
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* coherent with system memory.
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*
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* [...]
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*
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* Whenever the value of the Dynamic_State_Base_Addr,
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* Surface_State_Base_Addr are altered, the L1 state cache must be
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* invalidated to ensure the new surface or sampler state is fetched
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* from system memory.
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*
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* The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
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* which, according the PIPE_CONTROL instruction documentation in the
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* Broadwell PRM:
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*
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* Setting this bit is independent of any other bit in this packet.
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* This bit controls the invalidation of the L1 and L2 state caches
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* at the top of the pipe i.e. at the parsing time.
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*
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* Unfortunately, experimentation seems to indicate that state cache
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* invalidation through a PIPE_CONTROL does nothing whatsoever in
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* regards to surface state and binding tables. In stead, it seems that
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* invalidating the texture cache is what is actually needed.
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*
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* XXX: As far as we have been able to determine through
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* experimentation, shows that flush the texture cache appears to be
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* sufficient. The theory here is that all of the sampling/rendering
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* units cache the binding table in the texture cache. However, we have
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* yet to be able to actually confirm this.
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
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.TextureCacheInvalidationEnable = true);
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2015-07-15 20:09:52 +01:00
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}
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2015-07-30 22:59:02 +01:00
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VkResult anv_BeginCommandBuffer(
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VkCmdBuffer cmdBuffer,
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const VkCmdBufferBeginInfo* pBeginInfo)
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2015-07-15 20:09:52 +01:00
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{
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2015-07-30 22:59:02 +01:00
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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cmd_buffer->opt_flags = pBeginInfo->flags;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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if (cmd_buffer->level == VK_CMD_BUFFER_LEVEL_SECONDARY) {
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cmd_buffer->state.framebuffer =
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anv_framebuffer_from_handle(pBeginInfo->framebuffer);
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cmd_buffer->state.pass =
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anv_render_pass_from_handle(pBeginInfo->renderPass);
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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/* FIXME: We shouldn't be starting on the first subpass */
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anv_cmd_buffer_begin_subpass(cmd_buffer,
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&cmd_buffer->state.pass->subpasses[0]);
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2015-07-15 20:09:52 +01:00
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}
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2015-07-30 22:59:02 +01:00
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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cmd_buffer->state.current_pipeline = UINT32_MAX;
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2015-07-15 20:09:52 +01:00
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return VK_SUCCESS;
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}
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2015-07-30 22:59:02 +01:00
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VkResult anv_EndCommandBuffer(
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VkCmdBuffer cmdBuffer)
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2015-07-15 20:09:52 +01:00
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{
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2015-07-30 22:59:02 +01:00
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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struct anv_device *device = cmd_buffer->device;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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anv_cmd_buffer_end_batch_buffer(cmd_buffer);
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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if (cmd_buffer->level == VK_CMD_BUFFER_LEVEL_PRIMARY) {
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/* The algorithm used to compute the validate list is not threadsafe as
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* it uses the bo->index field. We have to lock the device around it.
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* Fortunately, the chances for contention here are probably very low.
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*/
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pthread_mutex_lock(&device->mutex);
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anv_cmd_buffer_prepare_execbuf(cmd_buffer);
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pthread_mutex_unlock(&device->mutex);
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}
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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return VK_SUCCESS;
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2015-07-15 20:09:52 +01:00
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}
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2015-07-30 22:59:02 +01:00
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void anv_CmdBindPipeline(
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VkCmdBuffer cmdBuffer,
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VkPipelineBindPoint pipelineBindPoint,
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VkPipeline _pipeline)
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2015-07-15 20:09:52 +01:00
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{
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2015-07-30 22:59:02 +01:00
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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switch (pipelineBindPoint) {
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case VK_PIPELINE_BIND_POINT_COMPUTE:
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cmd_buffer->state.compute_pipeline = pipeline;
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cmd_buffer->state.compute_dirty |= ANV_CMD_BUFFER_PIPELINE_DIRTY;
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break;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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case VK_PIPELINE_BIND_POINT_GRAPHICS:
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cmd_buffer->state.pipeline = pipeline;
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cmd_buffer->state.vb_dirty |= pipeline->vb_used;
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cmd_buffer->state.dirty |= ANV_CMD_BUFFER_PIPELINE_DIRTY;
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break;
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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default:
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assert(!"invalid bind point");
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break;
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}
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2015-07-15 20:09:52 +01:00
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}
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2015-07-30 22:59:02 +01:00
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void anv_CmdBindDynamicViewportState(
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VkCmdBuffer cmdBuffer,
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VkDynamicViewportState dynamicViewportState)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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ANV_FROM_HANDLE(anv_dynamic_vp_state, vp_state, dynamicViewportState);
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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cmd_buffer->state.vp_state = vp_state;
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cmd_buffer->state.dirty |= ANV_CMD_BUFFER_VP_DIRTY;
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}
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void anv_CmdBindDynamicRasterState(
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VkCmdBuffer cmdBuffer,
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VkDynamicRasterState dynamicRasterState)
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2015-07-15 20:09:52 +01:00
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{
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2015-07-30 22:59:02 +01:00
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
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ANV_FROM_HANDLE(anv_dynamic_rs_state, rs_state, dynamicRasterState);
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2015-07-15 20:09:52 +01:00
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2015-07-30 22:59:02 +01:00
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cmd_buffer->state.rs_state = rs_state;
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cmd_buffer->state.dirty |= ANV_CMD_BUFFER_RS_DIRTY;
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}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdBindDynamicColorBlendState(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkDynamicColorBlendState dynamicColorBlendState)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_dynamic_cb_state, cb_state, dynamicColorBlendState);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.cb_state = cb_state;
|
|
|
|
cmd_buffer->state.dirty |= ANV_CMD_BUFFER_CB_DIRTY;
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdBindDynamicDepthStencilState(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkDynamicDepthStencilState dynamicDepthStencilState)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_dynamic_ds_state, ds_state, dynamicDepthStencilState);
|
|
|
|
|
|
|
|
cmd_buffer->state.ds_state = ds_state;
|
|
|
|
cmd_buffer->state.dirty |= ANV_CMD_BUFFER_DS_DIRTY;
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdBindDescriptorSets(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkPipelineBindPoint pipelineBindPoint,
|
|
|
|
VkPipelineLayout _layout,
|
|
|
|
uint32_t firstSet,
|
|
|
|
uint32_t setCount,
|
|
|
|
const VkDescriptorSet* pDescriptorSets,
|
|
|
|
uint32_t dynamicOffsetCount,
|
|
|
|
const uint32_t* pDynamicOffsets)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
|
|
|
|
struct anv_descriptor_set_layout *set_layout;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(firstSet + setCount < MAX_SETS);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
uint32_t dynamic_slot = 0;
|
|
|
|
for (uint32_t i = 0; i < setCount; i++) {
|
|
|
|
ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
|
|
|
|
set_layout = layout->set[firstSet + i].layout;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.descriptors[firstSet + i].set = set;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(set_layout->num_dynamic_buffers <
|
|
|
|
ARRAY_SIZE(cmd_buffer->state.descriptors[0].dynamic_offsets));
|
|
|
|
memcpy(cmd_buffer->state.descriptors[firstSet + i].dynamic_offsets,
|
|
|
|
pDynamicOffsets + dynamic_slot,
|
|
|
|
set_layout->num_dynamic_buffers * sizeof(*pDynamicOffsets));
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
dynamic_slot += set_layout->num_dynamic_buffers;
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdBindIndexBuffer(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset,
|
|
|
|
VkIndexType indexType)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static const uint32_t vk_to_gen_index_type[] = {
|
|
|
|
[VK_INDEX_TYPE_UINT16] = INDEX_WORD,
|
|
|
|
[VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
|
|
|
|
};
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
struct GEN8_3DSTATE_VF vf = {
|
|
|
|
GEN8_3DSTATE_VF_header,
|
|
|
|
.CutIndex = (indexType == VK_INDEX_TYPE_UINT16) ? UINT16_MAX : UINT32_MAX,
|
|
|
|
};
|
|
|
|
GEN8_3DSTATE_VF_pack(NULL, cmd_buffer->state.state_vf, &vf);
|
2015-07-29 19:57:44 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.dirty |= ANV_CMD_BUFFER_INDEX_BUFFER_DIRTY;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_INDEX_BUFFER,
|
|
|
|
.IndexFormat = vk_to_gen_index_type[indexType],
|
|
|
|
.MemoryObjectControlState = GEN8_MOCS,
|
|
|
|
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
|
|
|
.BufferSize = buffer->size - offset);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdBindVertexBuffers(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
uint32_t startBinding,
|
|
|
|
uint32_t bindingCount,
|
|
|
|
const VkBuffer* pBuffers,
|
|
|
|
const VkDeviceSize* pOffsets)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
|
2015-07-29 19:57:44 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* We have to defer setting up vertex buffer since we need the buffer
|
|
|
|
* stride from the pipeline. */
|
2015-07-29 19:57:44 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(startBinding + bindingCount < MAX_VBS);
|
|
|
|
for (uint32_t i = 0; i < bindingCount; i++) {
|
|
|
|
vb[startBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
|
|
|
|
vb[startBinding + i].offset = pOffsets[i];
|
|
|
|
cmd_buffer->state.vb_dirty |= 1 << (startBinding + i);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-29 22:05:06 +01:00
|
|
|
static VkResult
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
unsigned stage, struct anv_state *bt_state)
|
2015-07-29 22:05:06 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
|
|
struct anv_subpass *subpass = cmd_buffer->state.subpass;
|
|
|
|
struct anv_pipeline_layout *layout;
|
|
|
|
uint32_t attachments, bias, size;
|
|
|
|
|
|
|
|
if (stage == VK_SHADER_STAGE_COMPUTE)
|
|
|
|
layout = cmd_buffer->state.compute_pipeline->layout;
|
|
|
|
else
|
|
|
|
layout = cmd_buffer->state.pipeline->layout;
|
|
|
|
|
|
|
|
if (stage == VK_SHADER_STAGE_FRAGMENT) {
|
|
|
|
bias = MAX_RTS;
|
|
|
|
attachments = subpass->color_count;
|
|
|
|
} else {
|
|
|
|
bias = 0;
|
|
|
|
attachments = 0;
|
|
|
|
}
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* This is a little awkward: layout can be NULL but we still have to
|
|
|
|
* allocate and set a binding table for the PS stage for render
|
|
|
|
* targets. */
|
|
|
|
uint32_t surface_count = layout ? layout->stage[stage].surface_count : 0;
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (attachments + surface_count == 0)
|
|
|
|
return VK_SUCCESS;
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
size = (bias + surface_count) * sizeof(uint32_t);
|
|
|
|
*bt_state = anv_cmd_buffer_alloc_surface_state(cmd_buffer, size, 32);
|
|
|
|
uint32_t *bt_map = bt_state->map;
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (bt_state->map == NULL)
|
|
|
|
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* This is highly annoying. The Vulkan spec puts the depth-stencil
|
|
|
|
* attachments in with the color attachments. Unfortunately, thanks to
|
|
|
|
* other aspects of the API, we cana't really saparate them before this
|
|
|
|
* point. Therefore, we have to walk all of the attachments but only
|
|
|
|
* put the color attachments into the binding table.
|
|
|
|
*/
|
|
|
|
for (uint32_t a = 0; a < attachments; a++) {
|
|
|
|
const struct anv_attachment_view *attachment =
|
|
|
|
fb->attachments[subpass->color_attachments[a]];
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(attachment->attachment_type == ANV_ATTACHMENT_VIEW_TYPE_COLOR);
|
|
|
|
const struct anv_color_attachment_view *view =
|
|
|
|
(const struct anv_color_attachment_view *)attachment;
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_state state =
|
|
|
|
anv_cmd_buffer_alloc_surface_state(cmd_buffer, 64, 64);
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (state.map == NULL)
|
|
|
|
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
|
2015-07-29 22:05:06 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
memcpy(state.map, view->view.surface_state.map, 64);
|
|
|
|
|
|
|
|
/* The address goes in dwords 8 and 9 of the SURFACE_STATE */
|
|
|
|
*(uint64_t *)(state.map + 8 * 4) =
|
|
|
|
anv_reloc_list_add(anv_cmd_buffer_current_surface_relocs(cmd_buffer),
|
|
|
|
cmd_buffer->device,
|
|
|
|
state.offset + 8 * 4,
|
|
|
|
view->view.bo, view->view.offset);
|
|
|
|
|
|
|
|
bt_map[a] = state.offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (layout == NULL)
|
|
|
|
return VK_SUCCESS;
|
|
|
|
|
|
|
|
for (uint32_t set = 0; set < layout->num_sets; set++) {
|
|
|
|
struct anv_descriptor_set_binding *d = &cmd_buffer->state.descriptors[set];
|
|
|
|
struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
|
|
|
|
struct anv_descriptor_slot *surface_slots =
|
|
|
|
set_layout->stage[stage].surface_start;
|
|
|
|
|
|
|
|
uint32_t start = bias + layout->set[set].surface_start[stage];
|
|
|
|
|
|
|
|
for (uint32_t b = 0; b < set_layout->stage[stage].surface_count; b++) {
|
|
|
|
struct anv_surface_view *view =
|
|
|
|
d->set->descriptors[surface_slots[b].index].view;
|
|
|
|
|
|
|
|
if (!view)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
struct anv_state state =
|
|
|
|
anv_cmd_buffer_alloc_surface_state(cmd_buffer, 64, 64);
|
|
|
|
|
|
|
|
if (state.map == NULL)
|
|
|
|
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
|
|
|
|
|
|
|
|
uint32_t offset;
|
|
|
|
if (surface_slots[b].dynamic_slot >= 0) {
|
|
|
|
uint32_t dynamic_offset =
|
|
|
|
d->dynamic_offsets[surface_slots[b].dynamic_slot];
|
|
|
|
|
|
|
|
offset = view->offset + dynamic_offset;
|
|
|
|
anv_fill_buffer_surface_state(state.map, view->format, offset,
|
|
|
|
view->range - dynamic_offset);
|
|
|
|
} else {
|
|
|
|
offset = view->offset;
|
|
|
|
memcpy(state.map, view->surface_state.map, 64);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The address goes in dwords 8 and 9 of the SURFACE_STATE */
|
|
|
|
*(uint64_t *)(state.map + 8 * 4) =
|
|
|
|
anv_reloc_list_add(anv_cmd_buffer_current_surface_relocs(cmd_buffer),
|
|
|
|
cmd_buffer->device,
|
|
|
|
state.offset + 8 * 4,
|
|
|
|
view->bo, offset);
|
|
|
|
|
|
|
|
bt_map[start + b] = state.offset;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static VkResult
|
|
|
|
cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
unsigned stage, struct anv_state *state)
|
2015-07-30 19:36:48 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_pipeline_layout *layout;
|
|
|
|
uint32_t sampler_count;
|
|
|
|
|
|
|
|
if (stage == VK_SHADER_STAGE_COMPUTE)
|
|
|
|
layout = cmd_buffer->state.compute_pipeline->layout;
|
|
|
|
else
|
|
|
|
layout = cmd_buffer->state.pipeline->layout;
|
|
|
|
|
|
|
|
sampler_count = layout ? layout->stage[stage].sampler_count : 0;
|
|
|
|
if (sampler_count == 0)
|
|
|
|
return VK_SUCCESS;
|
|
|
|
|
|
|
|
uint32_t size = sampler_count * 16;
|
|
|
|
*state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 32);
|
|
|
|
|
|
|
|
if (state->map == NULL)
|
|
|
|
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
|
|
|
|
|
|
|
|
for (uint32_t set = 0; set < layout->num_sets; set++) {
|
|
|
|
struct anv_descriptor_set_binding *d = &cmd_buffer->state.descriptors[set];
|
|
|
|
struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
|
|
|
|
struct anv_descriptor_slot *sampler_slots =
|
|
|
|
set_layout->stage[stage].sampler_start;
|
|
|
|
|
|
|
|
uint32_t start = layout->set[set].sampler_start[stage];
|
|
|
|
|
|
|
|
for (uint32_t b = 0; b < set_layout->stage[stage].sampler_count; b++) {
|
|
|
|
struct anv_sampler *sampler =
|
|
|
|
d->set->descriptors[sampler_slots[b].index].sampler;
|
|
|
|
|
|
|
|
if (!sampler)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
memcpy(state->map + (start + b) * 16,
|
|
|
|
sampler->state, sizeof(sampler->state));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
2015-07-30 19:36:48 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static VkResult
|
|
|
|
flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, uint32_t stage)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_state surfaces = { 0, }, samplers = { 0, };
|
|
|
|
VkResult result;
|
|
|
|
|
|
|
|
result = cmd_buffer_emit_samplers(cmd_buffer, stage, &samplers);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
return result;
|
|
|
|
result = cmd_buffer_emit_binding_table(cmd_buffer, stage, &surfaces);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
return result;
|
|
|
|
|
|
|
|
static const uint32_t sampler_state_opcodes[] = {
|
|
|
|
[VK_SHADER_STAGE_VERTEX] = 43,
|
|
|
|
[VK_SHADER_STAGE_TESS_CONTROL] = 44, /* HS */
|
|
|
|
[VK_SHADER_STAGE_TESS_EVALUATION] = 45, /* DS */
|
|
|
|
[VK_SHADER_STAGE_GEOMETRY] = 46,
|
|
|
|
[VK_SHADER_STAGE_FRAGMENT] = 47,
|
|
|
|
[VK_SHADER_STAGE_COMPUTE] = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const uint32_t binding_table_opcodes[] = {
|
|
|
|
[VK_SHADER_STAGE_VERTEX] = 38,
|
|
|
|
[VK_SHADER_STAGE_TESS_CONTROL] = 39,
|
|
|
|
[VK_SHADER_STAGE_TESS_EVALUATION] = 40,
|
|
|
|
[VK_SHADER_STAGE_GEOMETRY] = 41,
|
|
|
|
[VK_SHADER_STAGE_FRAGMENT] = 42,
|
|
|
|
[VK_SHADER_STAGE_COMPUTE] = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (samplers.alloc_size > 0) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
|
|
GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS,
|
|
|
|
._3DCommandSubOpcode = sampler_state_opcodes[stage],
|
|
|
|
.PointertoVSSamplerState = samplers.offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (surfaces.alloc_size > 0) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
|
|
GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS,
|
|
|
|
._3DCommandSubOpcode = binding_table_opcodes[stage],
|
|
|
|
.PointertoVSBindingTable = surfaces.offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2015-07-30 22:59:02 +01:00
|
|
|
flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
uint32_t s, dirty = cmd_buffer->state.descriptors_dirty &
|
|
|
|
cmd_buffer->state.pipeline->active_stages;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 19:32:27 +01:00
|
|
|
VkResult result = VK_SUCCESS;
|
2015-07-30 22:59:02 +01:00
|
|
|
for_each_bit(s, dirty) {
|
|
|
|
result = flush_descriptor_set(cmd_buffer, s);
|
2015-07-30 19:32:27 +01:00
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (result != VK_SUCCESS) {
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
|
2015-07-30 19:32:27 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
result = anv_cmd_buffer_new_surface_state_bo(cmd_buffer);
|
|
|
|
assert(result == VK_SUCCESS);
|
2015-07-30 19:32:27 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* Re-emit state base addresses so we get the new surface state base
|
|
|
|
* address before we start emitting binding tables etc.
|
|
|
|
*/
|
|
|
|
anv_cmd_buffer_emit_state_base_address(cmd_buffer);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* Re-emit all active binding tables */
|
|
|
|
for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
|
|
|
|
result = flush_descriptor_set(cmd_buffer, s);
|
2015-07-29 01:47:04 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* It had better succeed this time */
|
|
|
|
assert(result == VK_SUCCESS);
|
|
|
|
}
|
|
|
|
}
|
2015-07-29 01:47:04 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.descriptors_dirty &= ~cmd_buffer->state.pipeline->active_stages;
|
2015-07-29 01:47:04 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static struct anv_state
|
|
|
|
anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
uint32_t *a, uint32_t dwords, uint32_t alignment)
|
2015-07-29 19:57:44 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_state state;
|
|
|
|
|
|
|
|
state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
|
|
|
dwords * 4, alignment);
|
|
|
|
memcpy(state.map, a, dwords * 4);
|
|
|
|
|
|
|
|
VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, dwords * 4));
|
|
|
|
|
|
|
|
return state;
|
2015-07-29 19:57:44 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static struct anv_state
|
|
|
|
anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
uint32_t *a, uint32_t *b,
|
|
|
|
uint32_t dwords, uint32_t alignment)
|
2015-07-30 19:34:58 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_state state;
|
|
|
|
uint32_t *p;
|
2015-07-30 19:34:58 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
|
|
|
|
dwords * 4, alignment);
|
|
|
|
p = state.map;
|
|
|
|
for (uint32_t i = 0; i < dwords; i++)
|
|
|
|
p[i] = a[i] | b[i];
|
2015-07-30 19:34:58 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
|
2015-07-30 19:34:58 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
return state;
|
2015-07-30 19:34:58 +01:00
|
|
|
}
|
|
|
|
|
2015-07-15 20:09:52 +01:00
|
|
|
static VkResult
|
2015-07-30 22:59:02 +01:00
|
|
|
flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_device *device = cmd_buffer->device;
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
|
|
|
struct anv_state surfaces = { 0, }, samplers = { 0, };
|
|
|
|
VkResult result;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
result = cmd_buffer_emit_samplers(cmd_buffer,
|
|
|
|
VK_SHADER_STAGE_COMPUTE, &samplers);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
return result;
|
|
|
|
result = cmd_buffer_emit_binding_table(cmd_buffer,
|
|
|
|
VK_SHADER_STAGE_COMPUTE, &surfaces);
|
2015-07-15 20:09:52 +01:00
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
return result;
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
struct GEN8_INTERFACE_DESCRIPTOR_DATA desc = {
|
|
|
|
.KernelStartPointer = pipeline->cs_simd,
|
|
|
|
.KernelStartPointerHigh = 0,
|
|
|
|
.BindingTablePointer = surfaces.offset,
|
|
|
|
.BindingTableEntryCount = 0,
|
|
|
|
.SamplerStatePointer = samplers.offset,
|
|
|
|
.SamplerCount = 0,
|
|
|
|
.NumberofThreadsinGPGPUThreadGroup = 0 /* FIXME: Really? */
|
|
|
|
};
|
2015-07-29 23:28:51 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
uint32_t size = GEN8_INTERFACE_DESCRIPTOR_DATA_length * sizeof(uint32_t);
|
|
|
|
struct anv_state state =
|
|
|
|
anv_state_pool_alloc(&device->dynamic_state_pool, size, 64);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
GEN8_INTERFACE_DESCRIPTOR_DATA_pack(NULL, state.map, &desc);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
|
|
|
|
.InterfaceDescriptorTotalLength = size,
|
|
|
|
.InterfaceDescriptorDataStartAddress = state.offset);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static void
|
|
|
|
anv_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
|
|
|
VkResult result;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.current_pipeline != GPGPU) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_PIPELINE_SELECT,
|
|
|
|
.PipelineSelection = GPGPU);
|
|
|
|
cmd_buffer->state.current_pipeline = GPGPU;
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.compute_dirty & ANV_CMD_BUFFER_PIPELINE_DIRTY)
|
|
|
|
anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
|
|
|
|
(cmd_buffer->state.compute_dirty & ANV_CMD_BUFFER_PIPELINE_DIRTY)) {
|
|
|
|
result = flush_compute_descriptor_set(cmd_buffer);
|
|
|
|
assert(result == VK_SUCCESS);
|
|
|
|
cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE;
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.compute_dirty = 0;
|
2015-07-16 00:33:47 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static void
|
|
|
|
anv_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
|
|
|
|
uint32_t *p;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.current_pipeline != _3D) {
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_PIPELINE_SELECT,
|
|
|
|
.PipelineSelection = _3D);
|
|
|
|
cmd_buffer->state.current_pipeline = _3D;
|
2015-07-29 23:28:51 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (vb_emit) {
|
|
|
|
const uint32_t num_buffers = __builtin_popcount(vb_emit);
|
|
|
|
const uint32_t num_dwords = 1 + num_buffers * 4;
|
|
|
|
|
|
|
|
p = anv_batch_emitn(&cmd_buffer->batch, num_dwords,
|
|
|
|
GEN8_3DSTATE_VERTEX_BUFFERS);
|
|
|
|
uint32_t vb, i = 0;
|
|
|
|
for_each_bit(vb, vb_emit) {
|
|
|
|
struct anv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
|
|
|
|
uint32_t offset = cmd_buffer->state.vertex_bindings[vb].offset;
|
|
|
|
|
|
|
|
struct GEN8_VERTEX_BUFFER_STATE state = {
|
|
|
|
.VertexBufferIndex = vb,
|
|
|
|
.MemoryObjectControlState = GEN8_MOCS,
|
|
|
|
.AddressModifyEnable = true,
|
|
|
|
.BufferPitch = pipeline->binding_stride[vb],
|
|
|
|
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
|
|
|
.BufferSize = buffer->size - offset
|
|
|
|
};
|
|
|
|
|
|
|
|
GEN8_VERTEX_BUFFER_STATE_pack(&cmd_buffer->batch, &p[1 + i * 4], &state);
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.dirty & ANV_CMD_BUFFER_PIPELINE_DIRTY) {
|
|
|
|
/* If somebody compiled a pipeline after starting a command buffer the
|
|
|
|
* scratch bo may have grown since we started this cmd buffer (and
|
|
|
|
* emitted STATE_BASE_ADDRESS). If we're binding that pipeline now,
|
|
|
|
* reemit STATE_BASE_ADDRESS so that we use the bigger scratch bo. */
|
|
|
|
if (cmd_buffer->state.scratch_size < pipeline->total_scratch)
|
|
|
|
anv_cmd_buffer_emit_state_base_address(cmd_buffer);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.descriptors_dirty)
|
|
|
|
flush_descriptor_sets(cmd_buffer);
|
|
|
|
|
|
|
|
if (cmd_buffer->state.dirty & ANV_CMD_BUFFER_VP_DIRTY) {
|
|
|
|
struct anv_dynamic_vp_state *vp_state = cmd_buffer->state.vp_state;
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_SCISSOR_STATE_POINTERS,
|
|
|
|
.ScissorRectPointer = vp_state->scissor.offset);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
|
|
|
|
.CCViewportPointer = vp_state->cc_vp.offset);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
|
|
|
|
.SFClipViewportPointer = vp_state->sf_clip_vp.offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_BUFFER_PIPELINE_DIRTY |
|
|
|
|
ANV_CMD_BUFFER_RS_DIRTY)) {
|
|
|
|
anv_batch_emit_merge(&cmd_buffer->batch,
|
|
|
|
cmd_buffer->state.rs_state->state_sf,
|
|
|
|
pipeline->state_sf);
|
|
|
|
anv_batch_emit_merge(&cmd_buffer->batch,
|
|
|
|
cmd_buffer->state.rs_state->state_raster,
|
|
|
|
pipeline->state_raster);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.ds_state &&
|
|
|
|
(cmd_buffer->state.dirty & (ANV_CMD_BUFFER_PIPELINE_DIRTY |
|
|
|
|
ANV_CMD_BUFFER_DS_DIRTY))) {
|
|
|
|
anv_batch_emit_merge(&cmd_buffer->batch,
|
|
|
|
cmd_buffer->state.ds_state->state_wm_depth_stencil,
|
|
|
|
pipeline->state_wm_depth_stencil);
|
|
|
|
}
|
2015-07-29 01:47:04 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_BUFFER_CB_DIRTY |
|
|
|
|
ANV_CMD_BUFFER_DS_DIRTY)) {
|
|
|
|
struct anv_state state;
|
|
|
|
if (cmd_buffer->state.ds_state == NULL)
|
|
|
|
state = anv_cmd_buffer_emit_dynamic(cmd_buffer,
|
|
|
|
cmd_buffer->state.cb_state->state_color_calc,
|
|
|
|
GEN8_COLOR_CALC_STATE_length, 64);
|
|
|
|
else if (cmd_buffer->state.cb_state == NULL)
|
|
|
|
state = anv_cmd_buffer_emit_dynamic(cmd_buffer,
|
|
|
|
cmd_buffer->state.ds_state->state_color_calc,
|
|
|
|
GEN8_COLOR_CALC_STATE_length, 64);
|
|
|
|
else
|
|
|
|
state = anv_cmd_buffer_merge_dynamic(cmd_buffer,
|
|
|
|
cmd_buffer->state.ds_state->state_color_calc,
|
|
|
|
cmd_buffer->state.cb_state->state_color_calc,
|
|
|
|
GEN8_COLOR_CALC_STATE_length, 64);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
|
|
GEN8_3DSTATE_CC_STATE_POINTERS,
|
|
|
|
.ColorCalcStatePointer = state.offset,
|
|
|
|
.ColorCalcStatePointerValid = true);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_BUFFER_PIPELINE_DIRTY |
|
|
|
|
ANV_CMD_BUFFER_INDEX_BUFFER_DIRTY)) {
|
|
|
|
anv_batch_emit_merge(&cmd_buffer->batch,
|
|
|
|
cmd_buffer->state.state_vf, pipeline->state_vf);
|
|
|
|
}
|
2015-07-29 01:47:04 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.vb_dirty &= ~vb_emit;
|
|
|
|
cmd_buffer->state.dirty = 0;
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdDraw(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
uint32_t firstVertex,
|
|
|
|
uint32_t vertexCount,
|
|
|
|
uint32_t firstInstance,
|
|
|
|
uint32_t instanceCount)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_flush_state(cmd_buffer);
|
2015-07-29 01:47:04 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DPRIMITIVE,
|
|
|
|
.VertexAccessType = SEQUENTIAL,
|
|
|
|
.VertexCountPerInstance = vertexCount,
|
|
|
|
.StartVertexLocation = firstVertex,
|
|
|
|
.InstanceCount = instanceCount,
|
|
|
|
.StartInstanceLocation = firstInstance,
|
|
|
|
.BaseVertexLocation = 0);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdDrawIndexed(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
uint32_t firstIndex,
|
|
|
|
uint32_t indexCount,
|
|
|
|
int32_t vertexOffset,
|
|
|
|
uint32_t firstInstance,
|
|
|
|
uint32_t instanceCount)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
2015-07-29 23:28:51 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_flush_state(cmd_buffer);
|
2015-07-29 23:28:51 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DPRIMITIVE,
|
|
|
|
.VertexAccessType = RANDOM,
|
|
|
|
.VertexCountPerInstance = indexCount,
|
|
|
|
.StartVertexLocation = firstIndex,
|
|
|
|
.InstanceCount = instanceCount,
|
|
|
|
.StartInstanceLocation = firstInstance,
|
|
|
|
.BaseVertexLocation = vertexOffset);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static void
|
|
|
|
anv_batch_lrm(struct anv_batch *batch,
|
|
|
|
uint32_t reg, struct anv_bo *bo, uint32_t offset)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GEN8_MI_LOAD_REGISTER_MEM,
|
|
|
|
.RegisterAddress = reg,
|
|
|
|
.MemoryAddress = { bo, offset });
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static void
|
|
|
|
anv_batch_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
|
|
|
|
{
|
|
|
|
anv_batch_emit(batch, GEN8_MI_LOAD_REGISTER_IMM,
|
|
|
|
.RegisterOffset = reg,
|
|
|
|
.DataDWord = imm);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* Auto-Draw / Indirect Registers */
|
|
|
|
#define GEN7_3DPRIM_END_OFFSET 0x2420
|
|
|
|
#define GEN7_3DPRIM_START_VERTEX 0x2430
|
|
|
|
#define GEN7_3DPRIM_VERTEX_COUNT 0x2434
|
|
|
|
#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
|
|
|
|
#define GEN7_3DPRIM_START_INSTANCE 0x243C
|
|
|
|
#define GEN7_3DPRIM_BASE_VERTEX 0x2440
|
|
|
|
|
|
|
|
void anv_CmdDrawIndirect(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset,
|
|
|
|
uint32_t count,
|
|
|
|
uint32_t stride)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
|
|
struct anv_bo *bo = buffer->bo;
|
|
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
|
|
|
|
anv_cmd_buffer_flush_state(cmd_buffer);
|
|
|
|
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 12);
|
|
|
|
anv_batch_lri(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, 0);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DPRIMITIVE,
|
|
|
|
.IndirectParameterEnable = true,
|
|
|
|
.VertexAccessType = SEQUENTIAL);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdDrawIndexedIndirect(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset,
|
|
|
|
uint32_t count,
|
|
|
|
uint32_t stride)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
|
|
struct anv_bo *bo = buffer->bo;
|
|
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
|
|
|
|
anv_cmd_buffer_flush_state(cmd_buffer);
|
|
|
|
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_VERTEX, bo, bo_offset + 8);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_BASE_VERTEX, bo, bo_offset + 12);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_START_INSTANCE, bo, bo_offset + 16);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DPRIMITIVE,
|
|
|
|
.IndirectParameterEnable = true,
|
|
|
|
.VertexAccessType = RANDOM);
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdDispatch(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
uint32_t x,
|
|
|
|
uint32_t y,
|
|
|
|
uint32_t z)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
|
|
|
struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
|
|
|
|
|
|
|
|
anv_cmd_buffer_flush_compute_state(cmd_buffer);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_GPGPU_WALKER,
|
|
|
|
.SIMDSize = prog_data->simd_size / 16,
|
|
|
|
.ThreadDepthCounterMaximum = 0,
|
|
|
|
.ThreadHeightCounterMaximum = 0,
|
|
|
|
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
|
|
|
|
.ThreadGroupIDXDimension = x,
|
|
|
|
.ThreadGroupIDYDimension = y,
|
|
|
|
.ThreadGroupIDZDimension = z,
|
|
|
|
.RightExecutionMask = pipeline->cs_right_mask,
|
|
|
|
.BottomExecutionMask = 0xffffffff);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_MEDIA_STATE_FLUSH);
|
|
|
|
}
|
2015-07-16 00:22:04 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
#define GPGPU_DISPATCHDIMX 0x2500
|
|
|
|
#define GPGPU_DISPATCHDIMY 0x2504
|
|
|
|
#define GPGPU_DISPATCHDIMZ 0x2508
|
2015-07-29 23:28:51 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdDispatchIndirect(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkBuffer _buffer,
|
|
|
|
VkDeviceSize offset)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
|
|
|
|
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
|
|
|
|
struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data;
|
|
|
|
struct anv_bo *bo = buffer->bo;
|
|
|
|
uint32_t bo_offset = buffer->offset + offset;
|
|
|
|
|
|
|
|
anv_cmd_buffer_flush_compute_state(cmd_buffer);
|
|
|
|
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4);
|
|
|
|
anv_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMZ, bo, bo_offset + 8);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_GPGPU_WALKER,
|
|
|
|
.IndirectParameterEnable = true,
|
|
|
|
.SIMDSize = prog_data->simd_size / 16,
|
|
|
|
.ThreadDepthCounterMaximum = 0,
|
|
|
|
.ThreadHeightCounterMaximum = 0,
|
|
|
|
.ThreadWidthCounterMaximum = pipeline->cs_thread_width_max,
|
|
|
|
.RightExecutionMask = pipeline->cs_right_mask,
|
|
|
|
.BottomExecutionMask = 0xffffffff);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_MEDIA_STATE_FLUSH);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdSetEvent(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkEvent event,
|
|
|
|
VkPipelineStageFlags stageMask)
|
|
|
|
{
|
|
|
|
stub();
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdResetEvent(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkEvent event,
|
|
|
|
VkPipelineStageFlags stageMask)
|
|
|
|
{
|
|
|
|
stub();
|
2015-07-27 22:23:56 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdWaitEvents(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
uint32_t eventCount,
|
|
|
|
const VkEvent* pEvents,
|
|
|
|
VkPipelineStageFlags srcStageMask,
|
|
|
|
VkPipelineStageFlags destStageMask,
|
|
|
|
uint32_t memBarrierCount,
|
|
|
|
const void* const* ppMemBarriers)
|
2015-07-27 22:23:56 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
stub();
|
|
|
|
}
|
2015-07-27 22:23:56 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdPipelineBarrier(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkPipelineStageFlags srcStageMask,
|
|
|
|
VkPipelineStageFlags destStageMask,
|
|
|
|
VkBool32 byRegion,
|
|
|
|
uint32_t memBarrierCount,
|
|
|
|
const void* const* ppMemBarriers)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
uint32_t b, *dw;
|
2015-07-27 22:23:56 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
struct GEN8_PIPE_CONTROL cmd = {
|
|
|
|
GEN8_PIPE_CONTROL_header,
|
|
|
|
.PostSyncOperation = NoWrite,
|
|
|
|
};
|
2015-07-27 22:23:56 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* XXX: I think waitEvent is a no-op on our HW. We should verify that. */
|
|
|
|
|
|
|
|
if (anv_clear_mask(&srcStageMask, VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT)) {
|
|
|
|
/* This is just what PIPE_CONTROL does */
|
2015-07-27 22:23:56 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (anv_clear_mask(&srcStageMask,
|
|
|
|
VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
|
|
|
|
VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
|
|
|
|
VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_TESS_CONTROL_SHADER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_TESS_EVALUATION_SHADER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
|
|
|
|
VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
|
|
|
|
VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT)) {
|
|
|
|
cmd.StallAtPixelScoreboard = true;
|
|
|
|
}
|
2015-07-29 19:57:44 +01:00
|
|
|
|
2015-07-29 23:28:51 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (anv_clear_mask(&srcStageMask,
|
|
|
|
VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_TRANSFER_BIT |
|
|
|
|
VK_PIPELINE_STAGE_TRANSITION_BIT)) {
|
|
|
|
cmd.CommandStreamerStallEnable = true;
|
|
|
|
}
|
2015-07-29 23:28:51 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
if (anv_clear_mask(&srcStageMask, VK_PIPELINE_STAGE_HOST_BIT)) {
|
|
|
|
anv_finishme("VK_PIPE_EVENT_CPU_SIGNAL_BIT");
|
|
|
|
}
|
2015-07-27 22:23:56 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* On our hardware, all stages will wait for execution as needed. */
|
|
|
|
(void)destStageMask;
|
2015-07-29 20:01:02 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* We checked all known VkPipeEventFlags. */
|
|
|
|
anv_assert(srcStageMask == 0);
|
2015-07-29 20:01:02 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* XXX: Right now, we're really dumb and just flush whatever categories
|
|
|
|
* the app asks for. One of these days we may make this a bit better
|
|
|
|
* but right now that's all the hardware allows for in most areas.
|
|
|
|
*/
|
|
|
|
VkMemoryOutputFlags out_flags = 0;
|
|
|
|
VkMemoryInputFlags in_flags = 0;
|
|
|
|
|
|
|
|
for (uint32_t i = 0; i < memBarrierCount; i++) {
|
|
|
|
const struct anv_common *common = ppMemBarriers[i];
|
|
|
|
switch (common->sType) {
|
|
|
|
case VK_STRUCTURE_TYPE_MEMORY_BARRIER: {
|
|
|
|
ANV_COMMON_TO_STRUCT(VkMemoryBarrier, barrier, common);
|
|
|
|
out_flags |= barrier->outputMask;
|
|
|
|
in_flags |= barrier->inputMask;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER: {
|
|
|
|
ANV_COMMON_TO_STRUCT(VkBufferMemoryBarrier, barrier, common);
|
|
|
|
out_flags |= barrier->outputMask;
|
|
|
|
in_flags |= barrier->inputMask;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER: {
|
|
|
|
ANV_COMMON_TO_STRUCT(VkImageMemoryBarrier, barrier, common);
|
|
|
|
out_flags |= barrier->outputMask;
|
|
|
|
in_flags |= barrier->inputMask;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
unreachable("Invalid memory barrier type");
|
|
|
|
}
|
|
|
|
}
|
2015-07-30 22:22:17 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
for_each_bit(b, out_flags) {
|
|
|
|
switch ((VkMemoryOutputFlags)(1 << b)) {
|
|
|
|
case VK_MEMORY_OUTPUT_HOST_WRITE_BIT:
|
|
|
|
break; /* FIXME: Little-core systems */
|
|
|
|
case VK_MEMORY_OUTPUT_SHADER_WRITE_BIT:
|
|
|
|
cmd.DCFlushEnable = true;
|
|
|
|
break;
|
|
|
|
case VK_MEMORY_OUTPUT_COLOR_ATTACHMENT_BIT:
|
|
|
|
cmd.RenderTargetCacheFlushEnable = true;
|
|
|
|
break;
|
|
|
|
case VK_MEMORY_OUTPUT_DEPTH_STENCIL_ATTACHMENT_BIT:
|
|
|
|
cmd.DepthCacheFlushEnable = true;
|
|
|
|
break;
|
|
|
|
case VK_MEMORY_OUTPUT_TRANSFER_BIT:
|
|
|
|
cmd.RenderTargetCacheFlushEnable = true;
|
|
|
|
cmd.DepthCacheFlushEnable = true;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("Invalid memory output flag");
|
2015-07-30 22:22:17 +01:00
|
|
|
}
|
2015-07-30 19:36:48 +01:00
|
|
|
}
|
2015-07-30 05:22:10 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
for_each_bit(b, out_flags) {
|
|
|
|
switch ((VkMemoryInputFlags)(1 << b)) {
|
|
|
|
case VK_MEMORY_INPUT_HOST_READ_BIT:
|
|
|
|
break; /* FIXME: Little-core systems */
|
|
|
|
case VK_MEMORY_INPUT_INDIRECT_COMMAND_BIT:
|
|
|
|
case VK_MEMORY_INPUT_INDEX_FETCH_BIT:
|
|
|
|
case VK_MEMORY_INPUT_VERTEX_ATTRIBUTE_FETCH_BIT:
|
|
|
|
cmd.VFCacheInvalidationEnable = true;
|
|
|
|
break;
|
|
|
|
case VK_MEMORY_INPUT_UNIFORM_READ_BIT:
|
|
|
|
cmd.ConstantCacheInvalidationEnable = true;
|
|
|
|
/* fallthrough */
|
|
|
|
case VK_MEMORY_INPUT_SHADER_READ_BIT:
|
|
|
|
cmd.DCFlushEnable = true;
|
|
|
|
cmd.TextureCacheInvalidationEnable = true;
|
|
|
|
break;
|
|
|
|
case VK_MEMORY_INPUT_COLOR_ATTACHMENT_BIT:
|
|
|
|
case VK_MEMORY_INPUT_DEPTH_STENCIL_ATTACHMENT_BIT:
|
|
|
|
break; /* XXX: Hunh? */
|
|
|
|
case VK_MEMORY_INPUT_TRANSFER_BIT:
|
|
|
|
cmd.TextureCacheInvalidationEnable = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2015-07-29 20:01:02 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
dw = anv_batch_emit_dwords(&cmd_buffer->batch, GEN8_PIPE_CONTROL_length);
|
|
|
|
GEN8_PIPE_CONTROL_pack(&cmd_buffer->batch, dw, &cmd);
|
2015-07-29 20:01:02 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdPushConstants(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkPipelineLayout layout,
|
|
|
|
VkShaderStageFlags stageFlags,
|
|
|
|
uint32_t start,
|
|
|
|
uint32_t length,
|
|
|
|
const void* values)
|
2015-07-30 19:36:48 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
stub();
|
|
|
|
}
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
static void
|
|
|
|
anv_cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
|
|
|
|
{
|
|
|
|
struct anv_subpass *subpass = cmd_buffer->state.subpass;
|
|
|
|
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
|
|
|
|
const struct anv_depth_stencil_view *view;
|
|
|
|
|
|
|
|
static const struct anv_depth_stencil_view null_view =
|
|
|
|
{ .depth_format = D16_UNORM, .depth_stride = 0, .stencil_stride = 0 };
|
|
|
|
|
|
|
|
if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
|
|
|
|
const struct anv_attachment_view *aview =
|
|
|
|
fb->attachments[subpass->depth_stencil_attachment];
|
|
|
|
assert(aview->attachment_type == ANV_ATTACHMENT_VIEW_TYPE_DEPTH_STENCIL);
|
|
|
|
view = (const struct anv_depth_stencil_view *)aview;
|
|
|
|
} else {
|
|
|
|
view = &null_view;
|
2015-07-30 19:36:48 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* FIXME: Implement the PMA stall W/A */
|
|
|
|
/* FIXME: Width and Height are wrong */
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_DEPTH_BUFFER,
|
|
|
|
.SurfaceType = SURFTYPE_2D,
|
|
|
|
.DepthWriteEnable = view->depth_stride > 0,
|
|
|
|
.StencilWriteEnable = view->stencil_stride > 0,
|
|
|
|
.HierarchicalDepthBufferEnable = false,
|
|
|
|
.SurfaceFormat = view->depth_format,
|
|
|
|
.SurfacePitch = view->depth_stride > 0 ? view->depth_stride - 1 : 0,
|
|
|
|
.SurfaceBaseAddress = { view->bo, view->depth_offset },
|
|
|
|
.Height = cmd_buffer->state.framebuffer->height - 1,
|
|
|
|
.Width = cmd_buffer->state.framebuffer->width - 1,
|
|
|
|
.LOD = 0,
|
|
|
|
.Depth = 1 - 1,
|
|
|
|
.MinimumArrayElement = 0,
|
|
|
|
.DepthBufferObjectControlState = GEN8_MOCS,
|
|
|
|
.RenderTargetViewExtent = 1 - 1,
|
|
|
|
.SurfaceQPitch = view->depth_qpitch >> 2);
|
|
|
|
|
|
|
|
/* Disable hierarchial depth buffers. */
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_HIER_DEPTH_BUFFER);
|
|
|
|
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_STENCIL_BUFFER,
|
|
|
|
.StencilBufferEnable = view->stencil_stride > 0,
|
|
|
|
.StencilBufferObjectControlState = GEN8_MOCS,
|
|
|
|
.SurfacePitch = view->stencil_stride > 0 ? view->stencil_stride - 1 : 0,
|
|
|
|
.SurfaceBaseAddress = { view->bo, view->stencil_offset },
|
|
|
|
.SurfaceQPitch = view->stencil_qpitch >> 2);
|
|
|
|
|
|
|
|
/* Clear the clear params. */
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_CLEAR_PARAMS);
|
2015-07-30 19:36:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
|
|
|
|
struct anv_subpass *subpass)
|
2015-07-30 19:36:48 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.subpass = subpass;
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_emit_depth_stencil(cmd_buffer);
|
|
|
|
}
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdBeginRenderPass(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
const VkRenderPassBeginInfo* pRenderPassBegin,
|
|
|
|
VkRenderPassContents contents)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
|
|
|
ANV_FROM_HANDLE(anv_render_pass, pass, pRenderPassBegin->renderPass);
|
|
|
|
ANV_FROM_HANDLE(anv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
cmd_buffer->state.framebuffer = framebuffer;
|
|
|
|
cmd_buffer->state.pass = pass;
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
const VkRect2D *render_area = &pRenderPassBegin->renderArea;
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_3DSTATE_DRAWING_RECTANGLE,
|
|
|
|
.ClippedDrawingRectangleYMin = render_area->offset.y,
|
|
|
|
.ClippedDrawingRectangleXMin = render_area->offset.x,
|
|
|
|
.ClippedDrawingRectangleYMax =
|
|
|
|
render_area->offset.y + render_area->extent.height - 1,
|
|
|
|
.ClippedDrawingRectangleXMax =
|
|
|
|
render_area->offset.x + render_area->extent.width - 1,
|
|
|
|
.DrawingRectangleOriginY = 0,
|
|
|
|
.DrawingRectangleOriginX = 0);
|
|
|
|
|
|
|
|
anv_cmd_buffer_clear_attachments(cmd_buffer, pass,
|
|
|
|
pRenderPassBegin->pAttachmentClearValues);
|
2015-07-30 19:36:48 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses);
|
2015-07-30 19:36:48 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdNextSubpass(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
VkRenderPassContents contents)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(cmd_buffer->level == VK_CMD_BUFFER_LEVEL_PRIMARY);
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1);
|
|
|
|
}
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdEndRenderPass(
|
|
|
|
VkCmdBuffer cmdBuffer)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer);
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
/* Emit a flushing pipe control at the end of a pass. This is kind of a
|
|
|
|
* hack but it ensures that render targets always actually get written.
|
|
|
|
* Eventually, we should do flushing based on image format transitions
|
|
|
|
* or something of that nature.
|
|
|
|
*/
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
|
|
|
|
.PostSyncOperation = NoWrite,
|
|
|
|
.RenderTargetCacheFlushEnable = true,
|
|
|
|
.InstructionCacheInvalidateEnable = true,
|
|
|
|
.DepthCacheFlushEnable = true,
|
|
|
|
.VFCacheInvalidationEnable = true,
|
|
|
|
.TextureCacheInvalidationEnable = true,
|
|
|
|
.CommandStreamerStallEnable = true);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
void anv_CmdExecuteCommands(
|
|
|
|
VkCmdBuffer cmdBuffer,
|
|
|
|
uint32_t cmdBuffersCount,
|
|
|
|
const VkCmdBuffer* pCmdBuffers)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, primary, cmdBuffer);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(primary->level == VK_CMD_BUFFER_LEVEL_PRIMARY);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_assert(primary->state.subpass == &primary->state.pass->subpasses[0]);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
for (uint32_t i = 0; i < cmdBuffersCount; i++) {
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_buffer, secondary, pCmdBuffers[i]);
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
assert(secondary->level == VK_CMD_BUFFER_LEVEL_SECONDARY);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_cmd_buffer_add_secondary(primary, secondary);
|
|
|
|
}
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
VkResult anv_CreateCommandPool(
|
|
|
|
VkDevice _device,
|
|
|
|
const VkCmdPoolCreateInfo* pCreateInfo,
|
|
|
|
VkCmdPool* pCmdPool)
|
2015-07-15 20:09:52 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_device, device, _device);
|
|
|
|
struct anv_cmd_pool *pool;
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
pool = anv_device_alloc(device, sizeof(*pool), 8,
|
|
|
|
VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
|
|
|
|
if (pool == NULL)
|
|
|
|
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
list_inithead(&pool->cmd_buffers);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
*pCmdPool = anv_cmd_pool_to_handle(pool);
|
|
|
|
|
|
|
|
return VK_SUCCESS;
|
2015-07-15 20:09:52 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
VkResult anv_DestroyCommandPool(
|
|
|
|
VkDevice _device,
|
|
|
|
VkCmdPool cmdPool)
|
2015-07-27 22:52:16 +01:00
|
|
|
{
|
2015-07-30 22:59:02 +01:00
|
|
|
ANV_FROM_HANDLE(anv_device, device, _device);
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_pool, pool, cmdPool);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_ResetCommandPool(_device, cmdPool, 0);
|
2015-07-15 20:09:52 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
anv_device_free(device, pool);
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
VkResult anv_ResetCommandPool(
|
|
|
|
VkDevice device,
|
|
|
|
VkCmdPool cmdPool,
|
|
|
|
VkCmdPoolResetFlags flags)
|
|
|
|
{
|
|
|
|
ANV_FROM_HANDLE(anv_cmd_pool, pool, cmdPool);
|
2015-07-29 23:13:21 +01:00
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
|
|
|
|
&pool->cmd_buffers, pool_link) {
|
|
|
|
anv_DestroyCommandBuffer(device, anv_cmd_buffer_to_handle(cmd_buffer));
|
2015-07-29 23:13:21 +01:00
|
|
|
}
|
|
|
|
|
2015-07-30 22:59:02 +01:00
|
|
|
return VK_SUCCESS;
|
2015-07-27 22:52:16 +01:00
|
|
|
}
|