2012-07-17 13:09:03 +01:00
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Christian König <christian.koenig@amd.com>
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*/
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#include "util/u_memory.h"
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#include "radeonsi_pipe.h"
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#include "radeonsi_pm4.h"
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#include "sid.h"
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#include "r600_hw_context_priv.h"
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#define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
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2012-08-02 13:30:06 +01:00
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void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
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{
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state->last_opcode = opcode;
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state->last_pm4 = state->ndw++;
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}
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void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
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{
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state->pm4[state->ndw++] = dw;
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}
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void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
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{
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unsigned count;
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count = state->ndw - state->last_pm4 - 2;
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state->pm4[state->last_pm4] = PKT3(state->last_opcode,
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count, predicate);
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assert(state->ndw <= SI_PM4_MAX_DW);
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}
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2012-07-17 13:09:03 +01:00
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void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
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{
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2012-08-02 13:30:06 +01:00
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unsigned opcode;
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2012-07-17 13:09:03 +01:00
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if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) {
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opcode = PKT3_SET_CONFIG_REG;
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reg -= SI_CONFIG_REG_OFFSET;
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} else if (reg >= SI_SH_REG_OFFSET && reg <= SI_SH_REG_END) {
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opcode = PKT3_SET_SH_REG;
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reg -= SI_SH_REG_OFFSET;
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} else if (reg >= SI_CONTEXT_REG_OFFSET && reg <= SI_CONTEXT_REG_END) {
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opcode = PKT3_SET_CONTEXT_REG;
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reg -= SI_CONTEXT_REG_OFFSET;
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} else {
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R600_ERR("Invalid register offset %08x!\n", reg);
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return;
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}
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reg >>= 2;
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if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
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2012-08-02 13:30:06 +01:00
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si_pm4_cmd_begin(state, opcode);
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si_pm4_cmd_add(state, reg);
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2012-07-17 13:09:03 +01:00
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}
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state->last_reg = reg;
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2012-08-02 13:30:06 +01:00
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si_pm4_cmd_add(state, val);
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si_pm4_cmd_end(state, false);
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2012-07-17 13:09:03 +01:00
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}
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void si_pm4_add_bo(struct si_pm4_state *state,
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2012-07-24 17:47:19 +01:00
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struct si_resource *bo,
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2012-07-17 13:09:03 +01:00
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enum radeon_bo_usage usage)
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{
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unsigned idx = state->nbo++;
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assert(idx < SI_PM4_MAX_BO);
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2012-07-24 17:47:19 +01:00
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si_resource_reference(&state->bo[idx], bo);
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2012-07-17 13:09:03 +01:00
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state->bo_usage[idx] = usage;
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}
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void si_pm4_inval_shader_cache(struct si_pm4_state *state)
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{
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state->cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
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state->cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
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}
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void si_pm4_inval_texture_cache(struct si_pm4_state *state)
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{
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state->cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
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}
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void si_pm4_inval_vertex_cache(struct si_pm4_state *state)
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{
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/* Some GPUs don't have the vertex cache and must use the texture cache instead. */
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state->cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
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}
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void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs)
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{
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state->cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1);
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state->cp_coher_cntl |= ((1 << nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT;
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}
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void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state)
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{
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state->cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1);
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}
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void si_pm4_free_state(struct r600_context *rctx,
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struct si_pm4_state *state,
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unsigned idx)
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{
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if (state == NULL)
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return;
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2012-08-02 15:15:40 +01:00
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if (idx != ~0 && rctx->emitted.array[idx] == state) {
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2012-07-17 13:09:03 +01:00
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rctx->emitted.array[idx] = NULL;
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}
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for (int i = 0; i < state->nbo; ++i) {
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2012-08-03 15:51:32 +01:00
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si_resource_reference(&state->bo[i], NULL);
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2012-07-17 13:09:03 +01:00
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}
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FREE(state);
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}
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2012-08-02 15:15:40 +01:00
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uint32_t si_pm4_sync_flags(struct r600_context *rctx)
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{
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uint32_t cp_coher_cntl = 0;
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for (int i = 0; i < NUMBER_OF_STATES; ++i) {
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struct si_pm4_state *state = rctx->queued.array[i];
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if (!state || rctx->emitted.array[i] == state)
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continue;
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cp_coher_cntl |= state->cp_coher_cntl;
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}
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return cp_coher_cntl;
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}
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2012-07-17 13:09:03 +01:00
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unsigned si_pm4_dirty_dw(struct r600_context *rctx)
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{
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unsigned count = 0;
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for (int i = 0; i < NUMBER_OF_STATES; ++i) {
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struct si_pm4_state *state = rctx->queued.array[i];
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if (!state || rctx->emitted.array[i] == state)
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continue;
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count += state->ndw;
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}
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return count;
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}
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2012-08-02 15:15:40 +01:00
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void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state)
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2012-07-17 13:09:03 +01:00
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{
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struct radeon_winsys_cs *cs = rctx->cs;
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2012-08-02 15:15:40 +01:00
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for (int i = 0; i < state->nbo; ++i) {
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r600_context_bo_reloc(rctx, state->bo[i],
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state->bo_usage[i]);
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}
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2012-07-17 13:09:03 +01:00
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2012-08-02 15:15:40 +01:00
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memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
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cs->cdw += state->ndw;
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}
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void si_pm4_emit_dirty(struct r600_context *rctx)
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{
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2012-07-17 13:09:03 +01:00
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for (int i = 0; i < NUMBER_OF_STATES; ++i) {
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struct si_pm4_state *state = rctx->queued.array[i];
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if (!state || rctx->emitted.array[i] == state)
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continue;
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2012-08-02 15:15:40 +01:00
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si_pm4_emit(rctx, state);
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2012-07-17 13:09:03 +01:00
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rctx->emitted.array[i] = state;
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}
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}
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void si_pm4_reset_emitted(struct r600_context *rctx)
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{
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memset(&rctx->emitted, 0, sizeof(rctx->emitted));
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}
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