2017-09-13 01:26:26 +01:00
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/**************************************************************************
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*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors:
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* Christian König <christian.koenig@amd.com>
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*
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*/
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#include <stdio.h>
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#include "pipe/p_video_codec.h"
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#include "util/u_video.h"
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#include "util/u_memory.h"
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#include "vl/vl_video_buffer.h"
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#include "r600_pipe_common.h"
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#include "radeon_video.h"
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#include "radeon_vce.h"
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#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
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#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
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#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
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#define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
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#define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
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#define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
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#define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
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#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
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#define FW_53 (53 << 24)
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2020-01-21 15:08:21 +00:00
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/* version specific function for getting parameters */
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static void (*get_pic_param)(struct rvce_encoder *enc,
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struct pipe_h264_enc_picture_desc *pic) = NULL;
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2017-09-13 01:26:26 +01:00
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/**
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* flush commands to the hardware
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*/
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static void flush(struct rvce_encoder *enc)
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{
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2020-11-29 09:09:02 +00:00
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enc->ws->cs_flush(&enc->cs, PIPE_FLUSH_ASYNC, NULL);
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2017-09-13 01:26:26 +01:00
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enc->task_info_idx = 0;
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enc->bs_idx = 0;
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}
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#if 0
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static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
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{
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2020-11-29 09:09:02 +00:00
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uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, &enc->cs, PIPE_MAP_READ_WRITE);
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2017-09-13 01:26:26 +01:00
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unsigned i = 0;
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fprintf(stderr, "\n");
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fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
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fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
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fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
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fprintf(stderr, "\n");
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enc->ws->buffer_unmap(fb->res->buf);
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}
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#endif
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/**
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* reset the CPB handling
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*/
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static void reset_cpb(struct rvce_encoder *enc)
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{
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unsigned i;
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2019-10-27 22:49:39 +00:00
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list_inithead(&enc->cpb_slots);
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2017-09-13 01:26:26 +01:00
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for (i = 0; i < enc->cpb_num; ++i) {
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struct rvce_cpb_slot *slot = &enc->cpb_array[i];
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slot->index = i;
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2020-12-01 10:04:16 +00:00
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slot->picture_type = PIPE_H2645_ENC_PICTURE_TYPE_SKIP;
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2017-09-13 01:26:26 +01:00
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slot->frame_num = 0;
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slot->pic_order_cnt = 0;
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2019-10-27 22:58:31 +00:00
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list_addtail(&slot->list, &enc->cpb_slots);
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2017-09-13 01:26:26 +01:00
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}
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}
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/**
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* sort l0 and l1 to the top of the list
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*/
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static void sort_cpb(struct rvce_encoder *enc)
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{
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struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
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LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
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2022-05-02 17:41:00 +01:00
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if (i->frame_num == enc->pic.ref_idx_l0_list[0])
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2017-09-13 01:26:26 +01:00
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l0 = i;
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2022-05-02 17:41:00 +01:00
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if (i->frame_num == enc->pic.ref_idx_l1_list[0])
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2017-09-13 01:26:26 +01:00
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l1 = i;
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2020-12-01 10:04:16 +00:00
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if (enc->pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P && l0)
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2017-09-13 01:26:26 +01:00
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break;
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2020-12-01 10:04:16 +00:00
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if (enc->pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B &&
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2017-09-13 01:26:26 +01:00
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l0 && l1)
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break;
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}
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if (l1) {
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2019-10-27 23:11:53 +00:00
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list_del(&l1->list);
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2019-10-27 23:03:21 +00:00
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list_add(&l1->list, &enc->cpb_slots);
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2017-09-13 01:26:26 +01:00
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}
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if (l0) {
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2019-10-27 23:11:53 +00:00
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list_del(&l0->list);
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2019-10-27 23:03:21 +00:00
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list_add(&l0->list, &enc->cpb_slots);
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2017-09-13 01:26:26 +01:00
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}
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}
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/**
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* get number of cpbs based on dpb
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*/
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static unsigned get_cpb_num(struct rvce_encoder *enc)
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{
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unsigned w = align(enc->base.width, 16) / 16;
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unsigned h = align(enc->base.height, 16) / 16;
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unsigned dpb;
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switch (enc->base.level) {
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case 10:
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dpb = 396;
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break;
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case 11:
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dpb = 900;
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break;
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case 12:
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case 13:
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case 20:
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dpb = 2376;
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break;
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case 21:
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dpb = 4752;
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break;
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case 22:
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case 30:
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dpb = 8100;
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break;
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case 31:
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dpb = 18000;
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break;
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case 32:
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dpb = 20480;
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break;
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case 40:
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case 41:
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dpb = 32768;
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break;
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case 42:
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dpb = 34816;
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break;
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case 50:
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dpb = 110400;
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break;
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default:
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case 51:
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case 52:
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dpb = 184320;
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break;
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}
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return MIN2(dpb / (w * h), 16);
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}
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/**
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* Get the slot for the currently encoded frame
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*/
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struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
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{
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2022-07-27 16:48:11 +01:00
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return list_entry(enc->cpb_slots.prev, struct rvce_cpb_slot, list);
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2017-09-13 01:26:26 +01:00
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}
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/**
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* Get the slot for L0
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*/
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struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
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{
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2022-07-27 16:48:11 +01:00
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return list_entry(enc->cpb_slots.next, struct rvce_cpb_slot, list);
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2017-09-13 01:26:26 +01:00
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}
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/**
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* Get the slot for L1
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*/
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struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
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{
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2022-07-27 16:48:11 +01:00
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return list_entry(enc->cpb_slots.next->next, struct rvce_cpb_slot, list);
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2017-09-13 01:26:26 +01:00
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}
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/**
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* Calculate the offsets into the CPB
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*/
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void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
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signed *luma_offset, signed *chroma_offset)
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{
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unsigned pitch, vpitch, fsize;
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2017-10-09 04:30:02 +01:00
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pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
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vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
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2017-09-13 01:26:26 +01:00
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fsize = pitch * (vpitch + vpitch / 2);
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*luma_offset = slot->index * fsize;
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*chroma_offset = *luma_offset + pitch * vpitch;
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}
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/**
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* destroy this video encoder
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*/
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static void rvce_destroy(struct pipe_video_codec *encoder)
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{
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struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
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if (enc->stream_handle) {
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struct rvid_buffer fb;
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rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
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enc->fb = &fb;
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enc->session(enc);
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enc->feedback(enc);
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enc->destroy(enc);
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flush(enc);
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rvid_destroy_buffer(&fb);
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}
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rvid_destroy_buffer(&enc->cpb);
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2020-11-29 09:09:02 +00:00
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enc->ws->cs_destroy(&enc->cs);
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2017-09-13 01:26:26 +01:00
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FREE(enc->cpb_array);
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FREE(enc);
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}
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static void rvce_begin_frame(struct pipe_video_codec *encoder,
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struct pipe_video_buffer *source,
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struct pipe_picture_desc *picture)
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{
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struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
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struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
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struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
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bool need_rate_control =
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2021-07-13 16:59:50 +01:00
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enc->pic.rate_ctrl[0].rate_ctrl_method != pic->rate_ctrl[0].rate_ctrl_method ||
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2017-09-13 01:26:26 +01:00
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enc->pic.quant_i_frames != pic->quant_i_frames ||
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enc->pic.quant_p_frames != pic->quant_p_frames ||
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enc->pic.quant_b_frames != pic->quant_b_frames;
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enc->pic = *pic;
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get_pic_param(enc, pic);
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enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
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enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
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2020-12-01 10:04:16 +00:00
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if (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
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2017-09-13 01:26:26 +01:00
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reset_cpb(enc);
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2020-12-01 10:04:16 +00:00
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else if (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P ||
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pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
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2017-09-13 01:26:26 +01:00
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sort_cpb(enc);
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if (!enc->stream_handle) {
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struct rvid_buffer fb;
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enc->stream_handle = rvid_alloc_stream_handle();
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rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
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enc->fb = &fb;
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enc->session(enc);
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enc->create(enc);
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enc->config(enc);
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enc->feedback(enc);
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flush(enc);
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//dump_feedback(enc, &fb);
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rvid_destroy_buffer(&fb);
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need_rate_control = false;
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}
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if (need_rate_control) {
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enc->session(enc);
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enc->config(enc);
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flush(enc);
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}
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}
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static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
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struct pipe_video_buffer *source,
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struct pipe_resource *destination,
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void **fb)
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{
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struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
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enc->get_buffer(destination, &enc->bs_handle, NULL);
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enc->bs_size = destination->width0;
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*fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
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if (!rvid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
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RVID_ERR("Can't create feedback buffer.\n");
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return;
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}
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2020-11-29 09:09:02 +00:00
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if (!radeon_emitted(&enc->cs, 0))
|
2017-09-13 01:26:26 +01:00
|
|
|
enc->session(enc);
|
|
|
|
enc->encode(enc);
|
|
|
|
enc->feedback(enc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rvce_end_frame(struct pipe_video_codec *encoder,
|
|
|
|
struct pipe_video_buffer *source,
|
|
|
|
struct pipe_picture_desc *picture)
|
|
|
|
{
|
|
|
|
struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
|
2022-07-27 16:48:11 +01:00
|
|
|
struct rvce_cpb_slot *slot = list_entry(enc->cpb_slots.prev,
|
|
|
|
struct rvce_cpb_slot,
|
|
|
|
list);
|
2017-09-13 01:26:26 +01:00
|
|
|
|
|
|
|
if (!enc->dual_inst || enc->bs_idx > 1)
|
|
|
|
flush(enc);
|
|
|
|
|
|
|
|
/* update the CPB backtrack with the just encoded frame */
|
|
|
|
slot->picture_type = enc->pic.picture_type;
|
|
|
|
slot->frame_num = enc->pic.frame_num;
|
|
|
|
slot->pic_order_cnt = enc->pic.pic_order_cnt;
|
|
|
|
if (!enc->pic.not_referenced) {
|
2019-10-27 23:11:53 +00:00
|
|
|
list_del(&slot->list);
|
2019-10-27 23:03:21 +00:00
|
|
|
list_add(&slot->list, &enc->cpb_slots);
|
2017-09-13 01:26:26 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rvce_get_feedback(struct pipe_video_codec *encoder,
|
|
|
|
void *feedback, unsigned *size)
|
|
|
|
{
|
|
|
|
struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
|
|
|
|
struct rvid_buffer *fb = feedback;
|
|
|
|
|
|
|
|
if (size) {
|
2021-03-23 22:33:41 +00:00
|
|
|
uint32_t *ptr = enc->ws->buffer_map(enc->ws,
|
2020-11-29 09:09:02 +00:00
|
|
|
fb->res->buf, &enc->cs,
|
2020-08-06 17:47:01 +01:00
|
|
|
PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
|
2017-09-13 01:26:26 +01:00
|
|
|
|
|
|
|
if (ptr[1]) {
|
|
|
|
*size = ptr[4] - ptr[9];
|
|
|
|
} else {
|
|
|
|
*size = 0;
|
|
|
|
}
|
|
|
|
|
2021-03-23 22:33:41 +00:00
|
|
|
enc->ws->buffer_unmap(enc->ws, fb->res->buf);
|
2017-09-13 01:26:26 +01:00
|
|
|
}
|
|
|
|
//dump_feedback(enc, fb);
|
|
|
|
rvid_destroy_buffer(fb);
|
|
|
|
FREE(fb);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* flush any outstanding command buffers to the hardware
|
|
|
|
*/
|
|
|
|
static void rvce_flush(struct pipe_video_codec *encoder)
|
|
|
|
{
|
|
|
|
struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
|
|
|
|
|
|
|
|
flush(enc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rvce_cs_flush(void *ctx, unsigned flags,
|
|
|
|
struct pipe_fence_handle **fence)
|
|
|
|
{
|
|
|
|
// just ignored
|
|
|
|
}
|
|
|
|
|
|
|
|
struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
|
|
|
|
const struct pipe_video_codec *templ,
|
|
|
|
struct radeon_winsys* ws,
|
|
|
|
rvce_get_buffer get_buffer)
|
|
|
|
{
|
|
|
|
struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
|
|
|
|
struct r600_common_context *rctx = (struct r600_common_context*)context;
|
|
|
|
struct rvce_encoder *enc;
|
|
|
|
struct pipe_video_buffer *tmp_buf, templat = {};
|
|
|
|
struct radeon_surf *tmp_surf;
|
|
|
|
unsigned cpb_size;
|
|
|
|
|
|
|
|
if (!rscreen->info.vce_fw_version) {
|
|
|
|
RVID_ERR("Kernel doesn't supports VCE!\n");
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
} else if (!rvce_is_fw_version_supported(rscreen)) {
|
|
|
|
RVID_ERR("Unsupported VCE fw version loaded!\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
enc = CALLOC_STRUCT(rvce_encoder);
|
|
|
|
if (!enc)
|
|
|
|
return NULL;
|
|
|
|
|
2022-07-08 01:08:43 +01:00
|
|
|
enc->use_vui = true;
|
2017-09-13 01:26:26 +01:00
|
|
|
|
|
|
|
enc->base = *templ;
|
|
|
|
enc->base.context = context;
|
|
|
|
|
|
|
|
enc->base.destroy = rvce_destroy;
|
|
|
|
enc->base.begin_frame = rvce_begin_frame;
|
|
|
|
enc->base.encode_bitstream = rvce_encode_bitstream;
|
|
|
|
enc->base.end_frame = rvce_end_frame;
|
|
|
|
enc->base.flush = rvce_flush;
|
|
|
|
enc->base.get_feedback = rvce_get_feedback;
|
|
|
|
enc->get_buffer = get_buffer;
|
|
|
|
|
|
|
|
enc->screen = context->screen;
|
|
|
|
enc->ws = ws;
|
2020-11-29 09:09:02 +00:00
|
|
|
|
2022-05-05 18:49:29 +01:00
|
|
|
if (!ws->cs_create(&enc->cs, rctx->ctx, AMD_IP_VCE, rvce_cs_flush, enc, false)) {
|
2017-09-13 01:26:26 +01:00
|
|
|
RVID_ERR("Can't get command submission context.\n");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
templat.buffer_format = PIPE_FORMAT_NV12;
|
|
|
|
templat.width = enc->base.width;
|
|
|
|
templat.height = enc->base.height;
|
|
|
|
templat.interlaced = false;
|
|
|
|
if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
|
|
|
|
RVID_ERR("Can't create video buffer.\n");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
enc->cpb_num = get_cpb_num(enc);
|
|
|
|
if (!enc->cpb_num)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
|
|
|
|
|
2017-10-09 04:30:02 +01:00
|
|
|
cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
|
|
|
|
align(tmp_surf->u.legacy.level[0].nblk_y, 32);
|
2017-09-13 01:26:26 +01:00
|
|
|
|
|
|
|
cpb_size = cpb_size * 3 / 2;
|
|
|
|
cpb_size = cpb_size * enc->cpb_num;
|
|
|
|
if (enc->dual_pipe)
|
|
|
|
cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
|
|
|
|
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
|
|
|
|
tmp_buf->destroy(tmp_buf);
|
|
|
|
if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
|
|
|
|
RVID_ERR("Can't create CPB buffer.\n");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
|
|
|
|
if (!enc->cpb_array)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
reset_cpb(enc);
|
|
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
return &enc->base;
|
|
|
|
|
|
|
|
error:
|
2020-11-29 09:09:02 +00:00
|
|
|
enc->ws->cs_destroy(&enc->cs);
|
2017-09-13 01:26:26 +01:00
|
|
|
|
|
|
|
rvid_destroy_buffer(&enc->cpb);
|
|
|
|
|
|
|
|
FREE(enc->cpb_array);
|
|
|
|
FREE(enc);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* check if kernel has the right fw version loaded
|
|
|
|
*/
|
|
|
|
bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
|
|
|
|
{
|
|
|
|
switch (rscreen->info.vce_fw_version) {
|
|
|
|
case FW_40_2_2:
|
|
|
|
case FW_50_0_1:
|
|
|
|
case FW_50_1_2:
|
|
|
|
case FW_50_10_2:
|
|
|
|
case FW_50_17_3:
|
|
|
|
case FW_52_0_3:
|
|
|
|
case FW_52_4_3:
|
|
|
|
case FW_52_8_3:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
if ((rscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
|
|
|
|
return true;
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Add the buffer as relocation to the current command submission
|
|
|
|
*/
|
|
|
|
void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
|
2021-10-22 04:17:03 +01:00
|
|
|
unsigned usage, enum radeon_bo_domain domain,
|
2017-09-13 01:26:26 +01:00
|
|
|
signed offset)
|
|
|
|
{
|
|
|
|
int reloc_idx;
|
|
|
|
|
2020-11-29 09:09:02 +00:00
|
|
|
reloc_idx = enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
|
2021-10-22 04:17:03 +01:00
|
|
|
domain);
|
2017-09-13 01:26:26 +01:00
|
|
|
if (enc->use_vm) {
|
|
|
|
uint64_t addr;
|
|
|
|
addr = enc->ws->buffer_get_virtual_address(buf);
|
|
|
|
addr = addr + offset;
|
|
|
|
RVCE_CS(addr >> 32);
|
|
|
|
RVCE_CS(addr);
|
|
|
|
} else {
|
|
|
|
offset += enc->ws->buffer_get_reloc_offset(buf);
|
|
|
|
RVCE_CS(reloc_idx * 4);
|
|
|
|
RVCE_CS(offset);
|
|
|
|
}
|
|
|
|
}
|